Dear TI team
I am evaluating the circuit of the attached block with the DAC80502 on it.
At this time, the 3.3V starts faster than the 5V that drives the DAC80502, so the potential of SCLK/SDIN/XSYNC may momentarily exceed VDD+0.3V.
Still, according to the absolute maximum ratings, each pin of the DAC80502 can withstand up to ±10mA current at the device input during fault conditions, so I think it's okay.
Is the above understanding correct?
Best Regards,
Taroimo