ADC12DJ5200RF: TRF1208-ADC12DJ5200RFEVM sync toggling

Hi KLN,

Here are a few points to look at and verify:

1. An invalid sysref frequency is the most common issue for constant re-sync after successfully exiting CGS and ILAS phase. We checked the calculation and 10MHz is a valid sysref freq. Keep in mind 40MHz is max so any integer divide of 40MHz is legal.
2. Other ideas, its possible you have bad signal integrity, this can cause loss of link but given this is on our EVM, I would doubt it unless connected through another FMC extension cable? Please confirm.
3. Please try increasing the K value to increase elastic buffer, but considering you are getting to the data phase (past ILAS), this shouldn’t be the issue.
4. Can you please let us know the signal generator is decent? and not randomly adding an extra clock to the ADC?
5. The other possibility is that the SYSREF receiver isn’t configured correctly. Or you don’t have clean timing closure at 320MHz, which is causing errors on the receiver side.
6. Please send over the configuration file so that we can verify that the LMK sysref output is indeed actually10MHz also. Has this actually been measured with an oscope from the LMK? It may be setup wrong.

Regards,

Rob

Hi  Rob Reeder

Thanks for your response.

Rob Reeder said:

An invalid sysref frequency is the most common issue for constant re-sync after successfully exiting CGS and ILAS phase. We checked the calculation and 10MHz is a valid sysref freq. Keep in mind 40MHz is max so any integer divide of 40MHz is legal.

Yes, This has been followed. i have attached the screenshot of SYSREF which we measure at the ADC SYSREF_in

Rob Reeder said:

Other ideas, its possible you have bad signal integrity, this can cause loss of link but given this is on our EVM, I would doubt it unless connected through another FMC extension cable? Please confirm.

ADC EVM is mounted on xilinx ZCU216 board FMC Connector directly. No extension cable is involved.

Rob Reeder said:

Please try increasing the K value to increase elastic buffer, but considering you are getting to the data phase (past ILAS), this shouldn’t be the issue.

We have tried increasing K Value, Still the same result

Rob Reeder said:

Can you please let us know the signal generator is decent? and not randomly adding an extra clock to the ADC?

We have checked Signal generator output on Spectrum Analyzer and It is clean clock .PFA

This has been measured at LMX Input clock (From External Signal Generator)

Rob Reeder said:

The other possibility is that the SYSREF receiver isn’t configured correctly. Or you don’t have clean timing closure at 320MHz, which is causing errors on the receiver side.

we have put SYSREF in the chipscope on the receiver end and measured it (it is 32 clock of 320MHz which is equivalent to 10MHz). PFA

Rob Reeder said:

Please send over the configuration file so that we can verify that the LMK sysref output is indeed actually10MHz also. Has this actually been measured with an oscope from the LMK? It may be setup wrong.

PFA for the configuration.

ADC_config_JMODE2_fs3200.cfg

Thanks.

KLN,

Thanks for sharing your configuration, we will try to replicate on our hardware. I'm not sure we have a Zync US+ with GTY transceiver dev kit in the lab, so we will likely test with Kintex US+ GTY using your ADC and clocking configuration.

Regards, Chase

Hi Chase W

We would appreciate if you could check and let us know at the earliest.

Thanks.

Hi KLN,

We will be sure to update at our earliest findings. Kindly await a response and thank you for your patience.

Regards, Chase