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ADC09QJ1300EVM: is it possible to evaluate ADC09QJ1300EVM using TSW14J58EVM?

Part Number: ADC09QJ1300EVM
Other Parts Discussed in Thread: TSW14J57EVM, , TSW14J58EVM, ADC12QJ1600EVM, LMK04828

Dear all,

 i am going to evaluate ADC09QJ1300EVM using TI's High Speed Data Capture/Pattern Generator Card; and TSW14J57EVM  is easy to use, but it seems that TSW14J57EVM reference design needs external 1.6Ghz clock 

connected with ADC09QJ1300EVM. 

Is it possible to evaluate ADC09QJ1300EVM using TSW14J58EVM? So that i can evaluate ADC using onboard 50MEG clocking mode instead of external clock mode.

Testing Equipment for external clock source for High Speed ADC applications is not available for me at the moment;

Thanks a lot~~

  • Le,

    Can you share what is making you say that an external 1.6GHz clock is required for the TSW14J57EVM? This device should work with both J57 and J58, however would have better coverage on J57. In no cases are any clocks generated on the FPGA capture board passed to the ADC EVM at all. It is the other way around. The ADC EVM will generate all required FPGA clocks. This is why I'm confused by how switching to TSW14J58 will solve this (issue?).

    Regards, Chase

  • Hi,Chase,thanks for your reply

    i got the message of  TSW14J57EVM's clock in the post "ADC12QJ1600EVM: Time_out_error when using internal clock" created by Finlay Clarke;

    And  suggested that TSW14J57 EVM does not support onboard clocking mode. Only TSW14J58 allows that option.

    Fig.3-1 of SLAU808 also shows the EVM setup with an external clock using signal Gen.

    in my opinion, onboard clock setup and external setup may have different firmware for the difference of system clock.

    I am not sure...

    I also connected TSW14J57EVM with ADC with onboard clock, but it did not work yet T_T;

    So I have to confirm that my clock setup is correct...

  • Le,

    I see the issue now. Typically, you can use onboard or external clock regardless of TSW14J57 or TSW14J58. The limitation of using onboard clock is that you are limited only to frequencies which are capable of being generated by the LMK04828 PLL2. The issue here is the firmware on the TSW14J57 for this device is expecting signal at FMC pins H4, H5, which is only being supplied by PLLREFO+/- passing through the SE_CLK 50MHz. Knowing you are limited to 50MHz onboard clock now, let's find out why it isn't working. Are you able to probe the output of the 50MHz oscillator Y2 and verify a 50MHz signal is present at R231?

    Regards, Chase 

  • Hi, Chase

    according to your reply, i can use TSW14J57 to evaluate ADC by changing ADC09QJ1300EVM's BOM, right?

    I had tested the oscillator Y2's waveform (just use probe) and it seems ok;

    in order to use onboard clocking mode, according to the ADC EVM' schematic,

    I should Remove C285 and C67,C69 and then populate C68, C2 and C3 with 0.1uF caps 

    Is there any other bom that needs to be changed in ADC's EVM?

    SLAU808 also suggests to remove C60 and C61 and populate R233 and R235 with 0.1uF caps when using onboard clock option;

    i am not sure if the available firmware can accept these changes....

    Thanks again for your help~

  • Le,

    The engineer who supports this device is currently OOO so I am trying to fill in as best as I can without being as familiar with this device. Thank you for being patient with me on this! My understanding is that onboard clocking mode utilizes the 50MHz VCXO that is supplying the SE_CLK input with a clock. As a result, I don't believe any modifications are required for this onboard clocking style of bring up. Let me check with our team. Stay tuned.

    Regards, Chase

  • appreciate your help~

    I am looking forward to your reply:)

  • Hello Le,

    To make the changes for onboard clocking you must make the following hardware changes to the ADC EVM board as you listed above...

    a. Remove C45, C46, C2 and C3 and populate C67 and C69

    The firmware changes you have to make are to the ADC when programming it through the device GUI. The TSW14J57 fw can stay the same.

    Best,

    Eric Kleckner

  • Hi, Eric ,thanks for your reply

    I had tried to run the EVM again,but the link is still failed.

    I was following the literature of SLAU808 by only removing C60 and C61 and populating R233 and R235 with 0.1uF caps;

    Then I opened the ADC's EVM GUI, and set the ADC using GUI. Fig1 ~ Fig4 show the ADC's Status without TSW14J57.

     The JESD_STAUS register is 0110 0101;

    EVMPLL

    CTRL

    Howerver, when i connected the ADC09QJ1300EVM with TSW14J57EVM, there is a time out error after upgrading the firmware(i used

    ADC12QJXX00_JMODE3);And the ADC's JESD link also failed.  The JESD_STAUS register is 0000 0101;

    can you help me fix the error?

    Thanks a lot~

  • HI Le,

    Can you confirm what TSW board you are using the J58 or J57. This on board clocking mode is only supported on the J58 so you must use that.

    Another thing you can check is to verify that the FPGA CLK generated by the ADC PLL is the correct frequency. In this case 312.5MHz.

    Best,

    Eric Kleckner

  • hi, Eric

    ok, i will follow your suggestion and use J58 instead of J57 later.

    Thanks for your reply.