Other Parts Discussed in Thread: TMS570LC4357
I am working on interfacing with two ADS131M08 devices using a TMS570lc4357 (SPI1) and having some odd behavior on the MISO lines. The design is configured so that it uses MibSPI parallel mode, clocking data out MOSI[0] to both devices and using MISO[0] and MISO[1] to receive the response. One or both of the ADS131M08 devices randomly clocks out one extra byte, shifting the entire 10 word frame by one byte. This results in the status/ack byte, CRC, and all data between being shifted by one byte. The following image is an example of a case where MISO[0] is correct, but MISO[1] has an extra byte shifted in. Interestingly, the MISO[1] device indicates that a reset recently occurred, while MISO[0] indicates that resynchronization occurred. The CRC of MISO[0] is correct and the CRC of MISO[1] is correct if you ignore the 0x04 that is shifted in seemingly erroneously. Another interesting observation is that the MISO[1] line goes high too early at the end of the frame.
The following image shows a later message where MISO[0] has an extra byte and when accounting for that extra byte the CRC 0xBD35 matches the calculated CRC when starting with 0x4106. The data within MISO[1] appears corrupted because the CRC does not check out. The MISO[0] signal appears to transition high at the end of the frame too early.
Any thoughts or ideas are welcome as this issue has stumped me for a few days. Thank you for your help.
