• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 163 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC5672A: Data line sharing when using multiple DAC5672A

JH Shin
Mastermind 8375 points
Part Number: DAC5672A

Hello,

When using multiple DAC5672A, please let us know which lines can be shared and which control lines need to be separated.

The customer plans to use at least 4 DAC5672As and wants to minimize the number of lines connected to the FPGA.

Thank you.

JH

  • 0
    TI__Intellectual 2340 points

    Hey JH, 

    All of the inputs on this DAC are CMOS compatible, meaning they can easily share control signals. If each DAC is operated in single-bus interleaved mode, only 14 CMOS inputs will be needed per dual channel DAC. If their system is to be synchronized, they could fan out SELECTIQ, WRTIQ, CLKIQ and RESETIQ between all four DACs. Same goes for dual bus mode. (Pins now CLKA, CLKB, WRTA and WRTB). They'll just want to make sure they meet timing requirements between the data and the clock strobes. 

    They would likely want to use some CMOS fan out buffers between the FPGA and DACs if they are operating at higher sample rates. 

    Regards, 

    Matt

  • 0 in reply to Matthew Kramer
    Mastermind 8375 points

    Hi Matthew,

    Thanks for your reply.

    Is there a way to share the data lines of 4 DAC7672As and separate the control lines to use it as an 8CH DAC?

    As the data lines are separated, the number of lines that need to be connected increases too much.

     - 14 CMOS inputs x 4 DAC = 56 CMOS Lines

    Regards,

    JH

  • 0 in reply to JH Shin
    TI__Intellectual 2340 points

    Hey JH, 

    You could, in theory have the CMOS data lines change state multiple times between strobes, allowing you to time-interleave at which time each DAC is updated. Its important to remember the CMOS data lines do have setup and hold times so you would not be able to update all the DAC's at their maximum rate off shared CMOS lines. You would also likely need to use a CMOS fan out buffer as the capacitance of the inputs would add up to increase the RC delay. 

    Regards, 

    Matt