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Trouble setting up ADS1256

Other Parts Discussed in Thread: ADS1256

II never see the DRDY bit in STATUS REGISTER (ADDRESS 00h) of the ADS1256 go high.

II power up the ADC, and then bring both the SYNC and RESET lines high.  I then lower the RESET pin for 500 microseconds, which is much longer than 4 CLKIN, before bringing it high again.  At that stage I read the registers.

 

I send the command 0x10 followed by 0x0A.  I then read all 11 registers and I get returned

register[0] = 30
register[1] = 1
register[2] = 20
register[3] = f0
register[4] = ef
register[5] = c2
register[6] = 0
register[7] = 0
register[8] = 0
register[9] = 0
register[a] = 0

I think these values all make sense other than register 0 which shows only 0x30 instead of 0x31.

I send the commands and read the registers without every raising CS.  The clock starts low.  I read on the falling edge of the clock.

When I look at the lines on the scope, the values look consistent with the values I read above.

I would expect the DRDY bit to be 1 in register 0 because I have not requested any conversion.  Does anyone know why this bit would be reading zero?

Oliver

  • Oliver,

    Welcome to the forums! After you initiate a RESET, the ADS1256 will initiate an auto-cal procedure.  When this completes, DRDY will go low.

    Best regards,

    Bob B

  • Bob,

    Thank you for the response.  After the auto cal procedure should I expect OFC1, OFC2, FSC0, FSC1, & FSC2 registers to be zero?

    The only register that seems to be non zero in OFC0.

    Oliver

     

    register[0] = 30
    register[1] = 1
    register[2] = 20
    register[3] = f0
    register[4] = ef
    register[5] = c2
    register[6] = 0
    register[7] = 0
    register[8] = 0
    register[9] = 0
    register[a] = 0

  • Hi Oliver,

    After an auto cal procedure, the registers you listed are going to be programmed with their Auto-cal result. Those results are generally not zero and I would expect them to slightly vary from part to part.

    As for the /DRDY bit, I would expect it to be low following a conversion which would follow after the calibration process completes. Try reading back the data and then reading register 0. After the data is read back, /DRDY returns high until new data is ready and register 0 should follow this procedure.

    Regards,

    Tony Calabria