I am having trouble understanding the datasheet (SBASAG1 - October 2021).
Table 8-63 states:
Activate low voltage PECL mode for DEVCLK. The internal
termination for each input pin (CLK+ and CLK–) becomes a 50-Ω
resistor to ground. There is no input common-mode self-biasing for
CLK± when DEVCLK_LVPECL_EN is set to 1.
Table 6-1 states (in the CLK+ entry):
Device (sampling) clock positive input or differential PLL reference clock negative input. The clock signal is
strongly recommended to be AC-coupled to this input for best performance. This differential input has an
internal 100-Ω differential termination and is self-biased to the optimal input common-mode voltage as long as
DEVCLK_LVPECL_EN is set to 0. This pin can be left disconnected if SE_CLK is used to apply the reference
clock when the PLL is used.
So, when DEVCLK_LVPECL_EN is 0, what termination is used internally?
If I wish to clock CLK+/- from an LVDS source, how should this bit be set?
Thanks
