Part Number: AFE58JD48
Hello everyone,If I use an Intel Stratix 10 series FPGA to synchronously receive data from 8 AFEs through the JESD204B interface subclass 1, how should I connect the clock to the AFEs and FPGA? I found that the LMK0482X chip only supports a maximum of 7 pairs of device clocks and SYSREF outputs. I'm not sure if I need to connect 8 pairs of device clocks and SYSREF to the AFEs, and additionally connect 1 pair of device clock and SYSREF to the FPGA. If so, the output of one LMK0482X chip would not be enough. All my 8 AFEs are operating in the same mode. Is there a way for me to replicate one pair of device clock and SYSREF into 8 identical sets and connect them to the 8 AFEs ?
