ADS127L21: M_CRC_ERR

Hi Theo,

You do need to allow for a delay after writing to any of the included registers and the MAIN_CRC register before writing 1b to the M_CRC_ERR bit in the STATUS2 register.  The ADC requires a finite amount of time to calculate the CRC when any of the registers are updated.  I do not have an exact time, but you should allow several clock cycles.

Please let me know if this clears the flag after a small delay.

Regards,
Keith Nicholas
Precision ADC Applications

Hi Theo,

Did you also include the MUX register (address 0x05h) in your CRC calculation?  Also, what is the value of the MUX (0x00?) and the REVID for your part.

Regards,
Keith

Hi Keith

This is my sequence:
1. I reset the device via SPI (128 * 0xff). Then I wait 10ms.
2. Start conversion in CONTROL_REG. 
3. Clear all ERR flags in the status register.
4. Write CONFIG3 to enable CRCs
5. Read DEVID to calculate CRC
6. Read REVID to calculate CRC
7. Write and read back MUX register and calculate CRC. Then wait 1ms.
8. .....
9. Write and read back CONFIG3 again and calculate CRC. Then wait 1ms.
10. .....
11. Write and read back GAIN_LSB and calculate CRC. Then wait 1ms.
12. Wirte and read back CRC register.  Then wait 10ms.
13. Wirte 0x01 to STATUS2 to reset M_CRC_ERR. Then wait 1ms.
14. Read STATUS2 to check M_CRC_ERR.

If i write to the ADS without waiting between writes I get errors. I have a devboard which i modified to 3.3V because I only need low-speed mode. REVID is 0x00. I also connected the modified board to the TI test board which came with devkit and it stil works.

Regards Theo 

Hi Keith

It kind of works now.
I switched to writing the FIR_BANK first with its CRC_REG and then I toggle the  REG_CRC bit in CONFIG3 as mentioned int the datasheet. After this I do the rest of the config. But it needs to run everything twice to get the M_CRC_ERR to be "0". I do only use wait timers after i wrote a CRC to its register now and no longer in between every write command. Oh and I removed step "2. Start conversion in CONTROL_REG". I now do that after a successful configuration.

Is there any information what would be the correct sequence and does low-speed mode have an effect on how long it takes to calculate the CRC?

Regards Theo

Hello Theo,

Here is the proposed order for Register Memory CRC:

1. Write to all Main program memory registers with required values.
2. Calculate CRC for Main program memory registers (including REG_CRC bit set to 1).
3. Write CRC value to MAIN_CRC register.
4. Write FIR coefficients to FIR_BANK with required values.
5. Calculate CRC for FIR coefficients
6. Write CRC value to FIR_CRC1 and FIR_CRC0 registers.
7. Write IIR coefficients to IIR_BANK with required values.
8. Calculate CRC for IIR coefficients.
9. Write CRC value to IIR_CRC register.
10. Write 0 to REG_CRC bit, and then write 1 to REG_CRC bit.
    1. This enables CRC check and clears the M_CRC_ERR bit, F_CRC_ERR bit, and I_CRC_ERR bit in the STATUS2 register as well as the CRC_ERR bit in STATUS1 register.
    2. If REG_CRC bit is already 0, you can just write 1 to REG_CRC bit, or keep the same flow by first writing 0 and then 1.  It is the 0->1 transition of the REG_CRC bit that both enables CRC check and clears all x_CRC_ERR bits to 0.

Regarding the time needed to calculate the CRC, I have not been able to determine the exact number, but it is based on a number of CLK cycles.  If you change from high-speed (f-CLK=25.6MHz) to low-speed and use the internal divide by 8, then the required delay does not change because the external clock frequency is the same.  However, if you do not use the internal dividers (no division) and instead change the external clock to f-CLK=3.2MHz, then the required delay time will increase by a factor of 8x.

Regards,
Keith