My customer wants to undersample an IF signal at 36 MHz, with a bandwidth of 1 MHz, sample it using a 36 MHz clock, and then get digital samples at 2.25 Msps, which will have a frequency range of about 0 – 1.1 MHz with an ADS1602 data converter. The only mention of this phenomenon in the ADS1602 data sheet is essentially a warning that it might happen inadvertently, so you had better filter the input so that no signals at frequencies around multiples of the clock frequency get into the ADC, or else you will have unwanted aliasing. In his case, he wants this to happen, but would like to have somebody at TI tell me this is OK to do, and maybe provide details, like what sort of clock jitter spec he should have...
THank you,
Frank
