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ADS1274: /SYNC effect frequency of /DRDY (data rate)

Jun Liu
Prodigy 60 points

Part Number: ADS1274

Dear expert,

I am recently using ads1274 for 4 channels acquisition.  But encounter a strange phenomenon about /SYNC.

The ads1274 was in SPI / TDM / Fixed, High Resolution mode. With CLK frequency 27M, the data rate and /DRDY frequency is about 52.7K, as this picture, it's good. (Yellow is DRDY, Blue is SCLK)

 

At this time, /SYNC pin is float. It's voltage is ~3.3V. 

If I apply low voltage to /SYNC (such as GND), the /DRDY will go to high, and SCLK disappear. It's OK too, since according to datasheet, /DRDY will go to high at the /SYNC falling edge, and my MCU will not produce SCLK without DRDY falling edge. If I let the /SYNC pin float again, /DRDY and SCLK signal came back normally. 

The strange phenomenon is, if I apply high voltage to /SYNC (such as VCC 3.3V), the /DRDY frequency decreased, about 420Hz, which is much lower than expected 52.7K. Of course SCLK goes well with normal /DRDY.

Further testing, I found some /DRDY is lost, like this picture, only two /DRDY signal was captured.  

So, my question is how can I control the /SYNC pin. It looks like I failed if I connect the pin to general IO pin of MCU directly.

Thanks, 

 

  • 0
    TI__Guru 51550 points

    Hello Jun,

    The /SYNC pin should always be driven either high (VCC=3.3V) or low (ground).  If the /SYNC pin or any other digital input pins are floating, then the ADC will not function correctly.  All of the below pins for SPI mode need to be connected or driven to IOVDD (assume it is 3.3V) or ground.

    After power-up and the supply voltages have settled to within the recommended voltage levels, make sure all digital input pins are driven to the appropriate logic level.  Then assert the /SYNC pin (pulse low) to properly reset the ADC.

    If possible, please send a picture of your schematic and I can double-check your connections.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0
    Prodigy 60 points

    Thanks Keith for your quick reply. I do make sure that all the digital input pins are driven.

    Further testing, I found the IO signal from my MCU to drive /SYNC pin was oscillating at the same rate as SCLK. And I guess the /SYNC detect circuit of ads1274  was very sensitive? If it found falling edge @/SYNC, then the /DRDY will go to high. Which cause the /DRDY cannot go to low as normal.

    So I add a capacitor to filter the IO signal from my MCU. With that, the /DRDY rate was OK now, about 52.7K.

  • 0 in reply to Jun Liu
    TI__Guru 51550 points

    Hi Jun,

    Glad you were able to get the ADC working correctly.

    Regards,
    Keith