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ADS1278 input driver

ruggero rossi
Prodigy 40 points
Other Parts Discussed in Thread: ADS1278, THS4521, OPA1632, OPA209

I'm starting to design a multichannel acquisition system based on the ADS1278. Sampling frequency is about 8000KHz, in high resolution mode. In the specific application it is very important to have very good near DC performances.

Looking at the datasheet of the suggested ADC driver (THS4521), I noticed that high frequency amplifier noise is very good, but the 1/f set point is quite high. At 10Hz we have about 105nV/sqrt(Hz)

The alternate driver (OPA1632), has incredible low noise at high frequency, but still 1/f starts quit high (At 1Hz noise level is 45nV/sqrt(Hz)). moreover the required power for this part is not negligible.

Are there other possible drivers, more suitable for a slow application?

I evaluated the possibility to build my own driver using standard OP AMP. Using two OPA209 I could simulate a driver with noise less than 10nV/sqrt(Hz), and 1/f set point under 10Hz (16nV/sqrt(Hz) at 1Hz, but still not dominant). However the bandwidth the OPA209 is limited to few MHz. Is it a problem? Today ADC drivers normally have a huge bandwidth, but I do not know the real reason for that.

Best regards,

Ruggero Rossi

  • 0
    TI__Guru**** 181521 points

    Hi Ruggero,

    If I understand correctly, your plan is to run the input fCLK of the ADS1278 at 8MHz, so that in high-res mode you'll have a data rate of ~15.6Ksps, is that right?  We've actually mounted some of the THS4521 devices on our ADS1278EVM and still meet the DC performance specs of the device (12uV RMS).  The power consumption of the OPA1632, which is the driver we used on the EVM, is pretty significant in comparison - using eight of the THS4521 devices (one per channel) consumes less power that one- channel using the OPA1632.

    Let me consult with my OpAmp folks to see what else we might have for you, meanwhile, I'll dig up some app notes on the bandwidth versus sampling and either post links here or put them on our FAQ page under the Design Notes tab of this forum.

  • 0 in reply to Tom Hendrick
    Prodigy 40 points

     

    Hi Tom

    > your plan is to run the input fCLK of the ADS1278 at 8MHz, so that in high-res mode you'll have a data rate of ~15.6Ksps, is that right?

    Sorry, the typo devil hit again. I intended 8KHz sampling rate, about 1MHz Fmod, about 4 MHz Fclk. Anyway, conclusion are not too different: With a band from 0.1Hz to 4KHz the 1/f component of the THS4521 is dominating, and the 1/f noise is the most difficult to treat.

     

    >and still meet the DC performance specs of the device (12uV RMS).

    I didn't pay attention at the units on fig. 8 of datasheet. Those are uV! This means a pk-pk noise of 35uV, ie 117 ADU (and Vnoise-rms of 5.3uV). In such a case, the THS4521 will fit the bill.

    >Let me consult with my OpAmp folks to see what else we might have for you,

    Thank you, it will be interesting anyway.

     >I'll dig up some app notes on the bandwidth versus sampling....

    This would be very useful, not only for me.

     

     Regards,

    Ruggero

  • 0 in reply to ruggero rossi
    Prodigy 40 points

    Hi Tom

    As a consequence of the correct interpretation of fig.8, now I need to increase effective resolution. One possibility seems to be increasing the reference from 2.5 to 3V. According to datasheet,  signal to noise ratio increase from 110 to 111dB (practically scaling the X axis of fig. 8 (in uV, not in ADU) of a factor 1.2).

    Do this have side effects? are the THS4521 still the right  input drivers?

    best regards,

    Ruggero

  • 0 in reply to ruggero rossi
    TI__Mastermind 43915 points

    Hi Ruggero,

    The only side effect of increasing the reference to that value is a limitation on the max fclk frequency. The fclk frequency sets the fmod frequency for the part which in turn determines at what rate the input sampling switch opens and closes as well as the frequency of how fast the Vref is sampled. As you increase the fclk frequency, you are decreasing the amount of time that the switch stays closed to charge the internal sampling cap for Vref and the input. We found that increasing fclk beyond 27MHz brings some concern that there may not be enough time for the internal sampling cap / internal Vref sampling cap to fully charge to 3V before it is switched out. I know that sounds somewhat confusing so feel free to ask any follow up questions.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Prodigy 40 points

    Thank you. Your description is indeed very clear.

    However it bring another question. In my application sampling frequency is low: about 8KHz (Fclk about 4.2MHz).

    Does make sense to increase the input capacitors (from AINP and AINN)?

    I believe suggested value on datasheet (2.2n) probably came from similar considerations, and increasing them (if possible) may positively affect resolution (if we have enough time to load them and we do not damage the input switches).

    regards,

    Ruggero Rossi

     

     

     

  • 0 in reply to ruggero rossi
    TI__Mastermind 43915 points

    Hi Ruggero,

    In my testing, I found that 1-3nF was the best size for the input capacitor with the ADS1278. As I went smaller than 1nF, I would experience some ringing on the line when the modulator goes to take a sample and when I went bigger than 3nF, the input signal would begin to damp. These tests I used a 27MHz fclk so the modulator frequency was a little over 6MHz. Since you are decreasing the master clock down to about 4.2MHz, you may be able to get by using a larger capacitor at the input but I have not tested it myself to be able to say what the biggest value is that would work. 

    Regards,

    Tony Calabria