ADC12D1600RF: ADC12D1600RF

Rajan Bedi

Expert 1595 points

Part Number: ADC12D1600RF

Hello,

Can the sampling clock inputs be driven directly using an LVPECL or CML XO?

thank you

over 2 years ago

0 Amy over 2 years ago

TI__Genius 15321 points

HI Rajan,

Pg. 59 of the datasheet in section 6.1.2 states: "The ADC12D1x00RF has a differential clock input, CLK+ and CLK-, which must be driven with an ACcoupled, differential clock signal. This provides the level shifting necessary to allow for the clock to be driven with LVDS, PECL, LVPECL, or CML levels. The clock inputs are internally terminated to 100-Ω differential and self-biased."

Regards, Amy

0 Rajan Bedi over 2 years ago in reply to Amy

Expert 1595 points

Hi Amy,

Can you recommend a high-power, differential, sinewave clock source, e.g. several dBm?

thank you

0 Amy over 2 years ago in reply to Rajan Bedi

TI__Genius 15321 points

Hi Rajan,

Please define high-power, do you have a certain number of dBm you need?

Are you looking for a stand-alone oscillator, or do you need a clocking chip recommendation?

Or, are you looking for a recommendation for an external signal generator?

Regards, Amy

0 Rajan Bedi over 2 years ago in reply to Amy

Expert 1595 points

Amy,

The ADC can accept a differential clock input power from -7 to +7 dBm and I want to clock it near its maximum to maximise performance at high frequency. LVPEC and CML can be considered, but differential sine wave would potentially produce larger amplitude ...