• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 128 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DATACONVERTERPRO-SW: About TriggerCLKDelays in AutomationDLL

ryota-miyamoto
Prodigy 120 points
Part Number: DATACONVERTERPRO-SW
Other Parts Discussed in Thread: TSW14J57EVM

I found the 'TriggerCLKDelay' option in AutomationDLL.

We are considering starting data acquisition by inputting a synchronization signal into the TSW14J57EVM.

Can we use 'TriggerCLKDelay' to initiate data capture after a certain number of milliseconds have elapsed since the synchronization signal is received?

  • 0
    TI__Mastermind 22030 points

    Hi Ryota,

    As mentioned in other post, yes, this is an 8-bit field and refers to # of reference clock periods. You will not be able to delay by milliseconds however due to 8-bit limit. For example, with reference clock of say 50MHz (which is very low and likely lower than the ref clock required for your particular mode), 255/50MHz = 5.1us. The reference clock would have to be in kHz range for this to work which is not an option. Instead, it would be better to adjust the trigger output which you are using to account for this delay. When the trigger is received, if the FPGA is "armed", then the data will be saved.

    Regards, Chase