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ADC3662: Clock jitter on DCLKIN

Antonio Climaco
Prodigy 60 points
Part Number: ADC3662


Dear all,

We are designing a board with the ADC3662 configured to use the internal DDC feature with complex decimation.

To simplify the design, we are considering to generate the DCLKIN clock with the FPGA internal PLL.

This clock is used only for the LVDS serial interface and not for the acquisition.

The FPGA is a Xilinx Spartan 7, and the Clock wizard is estimating the PLL output jitter to be greater than 300ps pk-pk.

The maximum jitter for this clock is 50ps in the datasheet, not specifying if it is RMS or pk-pk.

Are there any problems in a similar configuration?

What would happen if the jitter on DCLKIN is too high?

 

Thanks and best regards

Antonio Climaco

  • 0
    TI__Mastermind 23920 points

    Antonio,

    If the jitter is too high then the setup and hold time for the data interface may not be met. I believe the jitter in the datasheet is referring to pk-pk jitter and is 100ps. This specification is copied from the 125MSPS device measured in DDC bypass mode. What is the datarate for your application? I suspect that since you are in a decimation mode and using the 25MSPS device, then it will be acceptable. These clocks should be phase aligned with respect to each other so as long as you have the ability to delay the DCLKIN output from the FPGA then I suspect this will be no issue in your application

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 60 points

    Dear Chase,

    Thanks for the answer.

    In the datasheet is stated "The phase relationship between DCLKIN and the sampling clock is irrelevant but both clocks need to be frequency locked."

    This made me think that some kind of "buffer" exist between the two clock domains to allow this.

    If the phase relationship is important, and setup/hold time have to be respected, where can I find these parameters as I don't see them into the datasheet.

    The only parameter linking the two clock I see is "tPD Propagation delay: sampling clock falling edge to DCLK rising edge", but this is not giving me any constraint on DCLKIN.

    What are the actual requirements between Sampling Clock and  DCLKIN?

    The actual DCLKIN frequency is ~10MHz, but we may be not using the DDC in future and I would like not to exclude this option. 

    Thanks and best regards

  • +1 in reply to Antonio Climaco
    TI__Mastermind 23920 points

    Hi Antonio,

    Yes, correct, the phase can be arbitrary however they should not drift. I apologize for any confusion there. One problem we have noted is the data lane coupling onto the input can be sensitive. If there is any coupling, this can be resolved by adjusting the phase offset between the sample clock and DCLKIN. One thing you can do to avoid this is to use the half swing mode to reduce chances of coupling onto input and to avoid this potential issue altogether, you can route LVDS on internal or opposite layer from input routing. At 10MHz I believe there will be no issue with fpga for DCLKIN.

    Regards, Chase