ADC12DJ5200RF: Transport Layer reference design for AD12DJ5200 JMODE3 on xilinx KU115 FPGA.

vetrivel M

Prodigy 150 points

Part Number: ADC12DJ5200RF

Hi All,

I am using the AD12DJ5200 in my custom board. For this I am using JESD 204 PHY as well as JESD204 Link Layer.

I want to know, how to make samples out of it.

Configuration:

JMOED3

Lanes per Link(L) = 8

Octets per frame(F) = 8

Frames per multi-frame(K) = 32

JESD204 output width = 256bit

How to make the JESD204 core output to the following format.

Pls provide some reference design for the data alignment.

Thanks in advance.

--Vetrivel

over 2 years ago

0 Eric Kleckner over 2 years ago

TI__Expert 6210 points

Hi Vetrivel,

From the picture you shared it you can create samples directly from this. meaning for channel A there are 8 lanes and channel B there are 8 lanes, the first 8 samples will be spread across these 8 lanes and so on and so forth as the diagram shows. So to unpack these samples all you will need to do is de-interleave these samples from all 8 lanes and put them in the correct order.

Best,

Eric Kleckner

Data converters

Data converters forum

ADC12DJ5200RF: Transport Layer reference design for AD12DJ5200 JMODE3 on xilinx KU115 FPGA.