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ADC12DJ5200RF: JESD204 can't established normally

xiaxin
Prodigy 60 points
Part Number: ADC12DJ5200RF
Other Parts Discussed in Thread: LMX2594, LMK04832,

Hello,

I am using adc12dj5200,the clock frequency is 5000MHz that generated from lmx2594,and sysref frequecy is 31.25MHz that generated from lmk04832.also,the lmx2594's oscin also comes from lmx04832..After I config the registers to this device,I read back the register 0x028,it readback 0x64,and the jesd204b not transmits k28.5.The following is a list of my register configurations.

24'h0000_B0;//rst adc

sleep(1);//delay 1ms

24'h002b_15;

24'h0002_00;

24'h02c2_00;//. clear alarm_mask register
24'h0200_00;//. JESD_EN=0

24'h0061_00;//. CAL_EN=0

24'h0201_01;//jmode = 1

24'h0202_03; //KM1=K-1

24'h0213_07; // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples

24'h0060_01;//. input mux，select INA
24'h0204_00; // Use SYNCSE input, offset binary data, scrambler disabled

24'h0029_20;
24'h0029_60;
24'h0029_7e;//.Program SYSREF_RECV_EN=1, SYSREF_PROC_EN=1, SYSREF_ZOOM=1 and SYSREF_SEL=0
24'h0061_01;// Set CAL_EN (always before JESD_EN)

24'h0200_01; // Set JESD_EN (always after CAL_EN)
24'h006C_00;// Set CAL_SOFT_TRIG low to reset calibration state machine

24'h02c1_00;//. clear alarm register
24'h006C_01;// Set CAL_SOFT_TRIG high to enable calibration

and the jesd204 lane data as below.

could you give me some suggestions to solve this problem,Thanks a lot!

  • 0
    TI__Expert 6150 points

    Hello,

    Are you using the ADC12DJ5200RF EVM or is this on a custom setup. Can you also confirm the FPGA reference clock frequency you are sending to the FPGA.

    Thanks,

    Eric Kleckner

  • 0 in reply to Eric Kleckner
    Prodigy 60 points

    Hello,

    I use adc12dj5200rf on my own board,and the FPGA reference clock is 250MHz comes from lmk04832.

  • 0 in reply to Eric Kleckner
    Prodigy 60 points

    Hello,

    I found out it was caused by my unstable sampling clock and the sync signal has been successfully raised.but another issue is that I read back the register 0x208,it indicates 0x64.If the configuration is correct, it should be 0x6c, right?

  • 0 in reply to xiaxin
    TI__Expert 6150 points

    Hello Xiaxin,

    This is correct the JESD_STATUS register (0x208) should be returning 0x6c. The Linkup, SYNC_STATUS and PLL_LOCKED bits are getting set correctly which is good. The problem you are seeing is that the align bits and realign bits are not getting set. To fix this try enabling sysref_processing before you enable the sys_ref_receiver. you would have to break this line of code into multiple steps.

    "24'h0029_7e;//.Program SYSREF_RECV_EN=1, SYSREF_PROC_EN=1, SYSREF_ZOOM=1 and SYSREF_SEL=0"

    Then once both bits get set then you need to clear the realign bit and check that it is never set again. You can use this psudeo code to check this feature. One thing to be careful of is when you are clearing the realign bit it is a reset high, the align bit, which we do not want to reset is also a reset high. So if you do a read modify write to reset the realign bit you will also inadvertently reset the align bit as well.

    Function checks if the SYSREF frequency is correct as per the JESD link requirements
                First it checks the  realign bit. It should be set to '1'
                If set to '1', it will clear the bit and ensure it doesn't get set again
                If set to '0', it will exit saying it didn't find re-alignment
                This function assumes that aligned flag has already been validated
                Loop 100 times:
                    read re-align
                    if set to 0, read again, until 100 successful reads occur
                    if it ever sets as 1, exit loop and print that sysref frequency and jesd link requirements
                    don't match

    If you have any other questions let me know.

    Best,

    Eric Kleckner

  • 0 in reply to Eric Kleckner
    Prodigy 60 points

    Hello Kleckner,

    Now the value I read back from 0x208 is 0x7c,both of the align bit and  re-align bit are set.

    And where should I loop 100 times through the register?after write all register?

    Is there any other way to debug this issue?

    Regards,

    Xiaxin

  • 0 in reply to xiaxin
    TI__Expert 6150 points

    Hi Xiaxin,

    that’s good that the align and realign bits are getting set. this this means that the LMFC clock phase has been established by the sysref. Which is what should happen if the link is operating correctly. The next thing you need to do is reset the realign bit. By writing a 1 to that bit field, then you need to check that that bit never gets set to one again. This is where can loop a couple of times and check this. If the realign bit gets set again after resetting it this means that the JESD link dropped and had to be realigned again.

    best,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 60 points

    Hello Kleckner,

    I have tried to write re-align bit as 1,and loop 100 times to read it.now I get 0x6c.but the sync signal is awful as below.

    could you tell me how to solve it?

    Regards,

    Xiaxin

  • 0 in reply to xiaxin
    TI__Expert 6150 points

    Hello Xiaxin,

    Can you check that your LMFS on your FPGA matches what is programmed to the ADC when you set the JMODE you can use link to check the LMFS for the JMODE you are using it is table 7-23 on page 95

    www.ti.com/.../adc12dj5200rf.pdf

    Best,

    Eric Kleckner