Part Number: AFE58JD48
hello .
I use AFE58JD48 in my project，we need 0.25-28MHz bandwith 。AFE58JD48 can support up to 60MHz bandwith.But we set the PGA LFP @ 30m 40m 50m in low noise mode , we input a sigal check the bandwith but it seems that not work 。the bandwith is only about 0.25-21M @-3db。
we have set in low power mode,the setting register is below
REG_Init_Config[0] <= 24'hc5_4000 ;// VCA (Must write 1 bits)
REG_Init_Config[1] <= 24'hd0_0001 ;// VCA (Must write 1 bits)
REG_Init_Config[2] <= 24'hde_00c3 ;// VCA (Must write 1 bits)
REG_Init_Config[3] <= 24'hd1_588c;
// REG_Init_Config[3] <= 24'hde_00c3;
REG_Init_Config[4] <= 24'hdf_0040 ;// VCA (Must write 1 bits)
REG_Init_Config[5] <= 24'h1e_0003 ; // ADC Master Page (Must write 1 bits)
REG_Init_Config[6] <= 24'h12_0005 ; // Selecting Miscellaneous Page
REG_Init_Config[7] <= 24'h2a_0800 ; // ADC Miscellaneous Page (Must write 1 bits)
REG_Init_Config[8] <= 24'h12_0000 ; // De-selecting Miscellaneous Page
REG_Init_Config[9] <= 24'h11_ffff ; // PAGE SEL ADCx = 1 (Enable Page Select Bit)
REG_Init_Config[10] <= 24'h25_0002 ; // INIT BIT = 1, Must write 1 as part of initialization after power-up
REG_Init_Config[11] <= 24'h11_0000 ; // PAGE SEL ADCx = 0(Disable Page Select Bit)
REG_Init_Config[12] <= 24'h12_000A ; // PAGE SEL 8CH DIG1,PAGE SEL 8CH DIG2 = 1
REG_Init_Config[13] <= 24'h31_03c0 ; // PLL MODE = 80X. CTRL K=1, CTRL MODE = 1
REG_Init_Config[14] <= 24'h34_111f ; // JESD SUBCLASS = 2, JESD VERSION = 1, K = 32
REG_Init_Config[15] <= 24'h35_01C0 ; // L=2,CTRL L = 1, CTRL M = 1 per 8adc
REG_Init_Config[16] <= 24'h36_0007 ; // M = 8
REG_Init_Config[17] <= 24'h30_8002 ; //The MSB is transmitted first on serialized output data
REG_Init_Config[18] <= 24'h30_8006 ; // Disable Page Select
REG_Init_Config[19] <= 24'hce_0006 ;
REG_Init_Config[20] <= 24'he8_68dc ;
REG_Init_Config[21] <= 24'he9_0100 ; //vca
REG_Init_Config[22] <= 24'h12_0000 ;
REG_Init_Config[23] <= 24'h13_ffff ;
REG_Init_Config[24] <= 24'h25_64ca ;//hpf
REG_Init_Config[25] <= 24'h26_fd28 ;//hpf
REG_Init_Config[26] <= 24'h27_fa60 ;//hpf
REG_Init_Config[27] <= 24'h28_001e ;//hpf
REG_Init_Config[28] <= 24'h24_0002 ;//hpf
REG_Init_Config[29] <= 24'h20_0019 ;//hpf
REG_Init_Config[30] <= 24'h13_0000 ;
REG_Init_Config[31] <= 24'h12_0000 ;
there is any someting we get wrong ? except the PGA LPF ,is there other LPF we need to set ? thanks!
