ADS61B23: TEST PATTERN - DIGITAL RAMP

Hi Zlatko,

This datasheet does indicate output ramp should increment by one code on every cycle. I can check if we have hardware to test this in the lab. In the meantime, which output interface are you using? parallel CMOS or DDR LVDS? What is your clock frequency? 

If you place into toggle pattern instead of ramp, does the output alternate every 4 cycles as with ramp?

Regards, Chase

Hi Chase,

65 MHz clock frequency

CMOS parallel

I will try toggle pattern later today.

Cheers

Zlatko

Chase,

We have some questions about SPI registers.

We are using serial interface programming where RST is held low at all times other than when we initialize registers.

If you toggle RESET high or write to register 0x00 bit D4 to 1 what happens to the ADC after that?

Are all registers reset to zero value?

Is zero value default for every register?

In what mode is ADC after reset is issued.

Do we have to write to every register even if we are to write zero to it again?

Thanks.

Hi Zlatko,

If you write to register 0x00 bit 4 a software reset is applied, meaning all internal registers are reset and the bit self-clears to 0.

All registers are set to their default values, which could be 0. 

Pg. 12 of the user guide details the default mode: https://www.ti.com/lit/ug/slau206b/slau206b.pdf?ts=1695853109934&ref_url=https%253A%252F%252Fwww.google.com%252F 

If you are writing zero to a register, you can just write to that register.

Additionally, please confirm that you are writing 0x80 to configure the device in ramp mode. 

Please update us once you test out the toggle pattern. 

Regards, Amy

TI: All registers are set to their default values, which could be 0. 

Zlatko : What are the default values for all registers after RESET is issued? From your answer it implies that they could be 0. Does that imply that it also could be 1?

TI: Additionally, please confirm that you are writing 0x80 to configure the device in ramp mode. 

Zlatko : we are writing  d10  d09  d08  d07  d06  d05  d04  d03  d02  d01  d00

                                       0      0      0     1       0      0      0      0      0      0      0

Hi Zlatko,

Page 12 of the user guide states all the default registers along with an alternative value: 

https://www.ti.com/lit/ug/slau206b/slau206b.pdf?ts=1695853109934&ref_url=https%253A%252F%252Fwww.google.com%252F 

Based on this, you can correlate the default values to the register map in the datasheet (pg. 15) to understand what the default value will be: 

https://www.ti.com/lit/ds/symlink/ads61b23.pdf?ts=1696003392093&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FADS61B23

Additionally, that is the correct register write to put the device in ramp mode per the datasheet.

Regards, Amy

It seems that I am not getting my point across.

Page 12 in the EVAL USER GUIDE lists EVAL board defaults.

I am asking what are the register defaults for the ASC61B23 ADC IC after RESET is issued by toggling RST pin or writing 1 to register 0x00 bit D4.

As far as I can tell that formation is not in the data sheet.

That is why I have been asking this question.

Please provide answer for the question marked in red.

Zlatko

Hi Zlatko,

We do not have any hardware in our lab for this device so we cannot perform any readback. This device was released prior to us making it standard to include default register values in the datasheet, our apologies for that. Is your hardware capable of reading back serial interface? If so, I'd suggest to loop through all 8 of the registers to see which registers you will need to change during your configuration.

Regards, Chase 

Chase,

So if understand this correctly this is what we need to do.

Because default register values are unknown and there is no way to read them back from the part ,we have to write our desired configuration to every register at least once.

Can you confirm that this is the case?

Zlatko