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ADC32RF45: How to enable test pattern mode

Doug Wilson
Prodigy 35 points

Part Number: ADC32RF45

When we attempt to enable test patterns in the DDC by writing to register 37h nothing happens. It functions as if its operating normally. Also table 11 and table 190 give conflicting info about what bits to use.

I've tried with and without using the test pattern reset in 3A but that doesn't seem to help, and tried test pattern for all 0, all 1 and ramp

Register dump:

Master Page Regs:
0x20: 0x0000
0x32: 0x0000
0x39: 0x0050
0x3c: 0x0000
0x3d: 0x0005
0x57: 0x0010
0x58: 0x0000
0x5a: 0x0000
ADC Page Regs:
0x3f: 0x0000
0x42: 0x0003
Offset Correction Page Regs: (Channel A  Channel B)
0x68: 0x0042    0x0042
Digital Gain Page Regs: (Channel A       Channel B)
0xa6: 0x0000    0x0000
Main Digital Page Regs: (Channel A       Channel B)
0x00: 0x0000    0x0000
0xa2: 0x0008    0x0008
JESD Digital Page Regs: (Channel A       Channel B)
0x01: 0x0080    0x0080
0x02: 0x0000    0x0000
0x03: 0x0002    0x0002
0x04: 0x0000    0x0000
0x06: 0x0000    0x0000
0x07: 0x001f    0x001f
0x16: 0x0070    0x0070
0x17: 0x0000    0x0000
0x32: 0x0000    0x0000
0x33: 0x0000    0x0000
0x34: 0x0000    0x0000
0x35: 0x0000    0x0000
0x36: 0x0040    0x0000
0x37: 0x0002    0x0002
0x3c: 0x0001    0x0000
0x3e: 0x0060    0x0060
Decimation Filter Page Regs: (Channel A  Channel B)
0x00: 0x0001    0x0001
0x01: 0x0001    0x0001
0x02: 0x0000    0x0000
0x05: 0x0001    0x0001
0x06: 0x0000    0x0000
0x07: 0x0000    0x0000
0x08: 0x0000    0x0000
0x09: 0x0000    0x0000
0x0a: 0x0000    0x0000
0x0b: 0x0000    0x0000
0x0c: 0x0000    0x0000
0x0d: 0x0000    0x0000
0x0e: 0x0000    0x0000
0x0f: 0x0000    0x0000
0x10: 0x0000    0x0000
0x11: 0x0000    0x0000
0x14: 0x0000    0x0000
0x16: 0x0000    0x0000
0x1e: 0x0001    0x0001
0x1f: 0x0000    0x0000
0x33: 0x0000    0x0000
0x34: 0x0000    0x0000
0x35: 0x0000    0x0000
0x36: 0x0000    0x0000
0x37: 0x0010    0x0010
0x3a: 0x0001    0x0001
Power Detector Page Regs: (Channel A     Channel B)
0x00: 0x0000    0x0000
0x01: 0x0010    0x0010
0x02: 0x0000    0x0000
0x03: 0x0000    0x0000
0x07: 0x00e6    0x00e6
0x08: 0x00cc    0x00cc
0x09: 0x00b3    0x00b3
0x0a: 0x0099    0x0099
0x0b: 0x0000    0x0000
0x0c: 0x0000    0x0000
0x0d: 0x0000    0x0000
0x0e: 0x0000    0x0000
0x0f: 0x0000    0x0000
0x10: 0x0000    0x0000
0x11: 0x0000    0x0000
0x12: 0x0000    0x0000
0x13: 0x0000    0x0000
0x16: 0x0000    0x0000
0x17: 0x0000    0x0000
0x18: 0x0000    0x0000
0x19: 0x0000    0x0000
0x1a: 0x0000    0x0000
0x1d: 0x0000    0x0000
0x1e: 0x0000    0x0000
0x20: 0x0000    0x0000
0x21: 0x0000    0x0000
0x22: 0x0000    0x0000
0x23: 0x0000    0x0000
0x24: 0x0000    0x0000
0x25: 0x0000    0x0000
0x27: 0x0000    0x0000
0x2b: 0x0000    0x0000
0x33: 0x0005    0x0005
0x34: 0x000d    0x000d
0x35: 0x000e    0x000e
0x36: 0x000e    0x000e
0x37: 0x0000    0x0000
0x38: 0x0000    0x0000

  • 0
    TI__Mastermind 24550 points

    Hi Doug,

    I will be working on this for you. Can you confirm sample rate and operating mode? I think if you are using bypass mode you can only enable the 12 bit ramp pattern (if i recall correctly, decimation filter page 0x00 as 0x01 means ddc bypass mode, but my memory may be off). I can look deeper into register list tomorrow to find out what's going on. 

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 35 points

    According table 72, 0x1 means the decimation filter is enabled, and 0x0 means DDC disabled. However, this is the first iteration of our product using the DDC and our previous iterations had it bypassed so the chance of a mistake related to that is high.

  • 0 in reply to Doug Wilson
    TI__Mastermind 24550 points

    Hi Doug, you are correct. My memory was incorrect. I will set this up and look at this today. What is your sample rate? This looks like complex DDC by 6, is that correct?

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 35 points

    We are providing 3GHz to CLKIN and decimating by 6 complex (divide by 3 real). Please confirm that that this means the ADC will sample at 3Gsps, then decimate and send 1Gsps over JESD.

    We are intending to use LMFS 4211, single-band real output wide bandwidth (table 18).

  • +1 in reply to Doug Wilson
    TI__Mastermind 24550 points

    Hi Doug,

    I am able to set the output for ramp test pattern mode by first choosing the ramp pattern in register 0x37 (value 0x04) and then toggling the reset test pattern in register 0x3A from value 0x00 to 0x02. To return back to normal output data (write register 0x37 with value 0x00) and then toggle register 0x3A low and high again, then to disable changing of the test pattern, you can write register 0x3A as 0x00. I know this isn't so great in a paragraph format so please see writes below. 

    To enable ramp pattern:

    0x37  0x04  # Selects ramp pattern output
    0x3A  0x00  # Enables resetting of test pattern 
    0x3A  0x02  # Resets the test pattern output from normal operation to ramp mode, ramp data should be present now
    0x3A  0x00  # Locks output as ramp pattern output

    To disable ramp pattern:

    0x37  0x00  # Selects normal output
    0x3A  0x00  # Enables resetting of test pattern
    0x3A  0x02  # Resets the test pattern output from ramp mode to normal operation, normal data should be present now
    0x3A  0x00  # Locks output as normal output

    Note that the datasheet shows 0x3A[bit 0] as having to be high to enable the 0x3A[bit 1] toggle to take effect, however on my hardware I have noticed that 0x3A[bit 0] has to be LOW in order for the rising edge toggle of 0x3A[bit 1] to take effect. I have tested using your operating mode, real ddc-by-3 (Complex ddc-by-6, real output). Can you try this and revert back?

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 35 points

    Edit: the above instructions work without modification. I thought the following writes were required because of a mistake on my part.

    Those instructions initially didn't work but doing them after the following register writes:

    0x14 0x1

    0x16 0x1

    0x1f 0x1

    0x1e 0x0

    Then doing what you suggested it works. The values in the aforementioned writes are the values suggested by the ADC32RFxx EVM GUI that were different than what we already had.

  • 0 in reply to Doug Wilson
    TI__Mastermind 24550 points

    Hi Doug,

    Excellent! Glad to help. If you have any other questions, feel free to ask and we'll get them taken care of for you.

    Regards, Chase 

  • 0 in reply to Chase W
    TI__Mastermind 24550 points

    Hi Doug,

    Thanks for the edited post. This will help others down the road encountering similar issues.

    Regards, Chase