Part Number: AFE4960
Hello,
Support.
I'm sorry. I had a misunderstanding about this issue.
This issue is getting few sample.
RAC time period is right. 8mS @ COUNT_RAC = 1024.
CPU gets the data from the FIFO by polling method in 64mS cycle.
So we expect the about 8 samples at a time.
But we get the just only 4 samples at a time.
To get 8 samples at 8mS RAC in 64mS, what should we set to the registers??
the current Register setting is below.
COUNT_RAC=1024Dec. 8mS RAC time.
REG_NUM_TS=0 (Addr0xC4): the number of time slot =1
REG_NUM_ESAW=0 (Addr0xC4)
REG_NUM_BSAW=0 (Addr0xC4)
CONFIG_TS0=1 (Addr0xC2)
We expect getting the 8 samples in 64mS.
we get capture the FIFO timing.
The wave form is below.
RAC_RST=8mS.
NUM_TS0=0.
CONFIG_TS0=1.
Thus only 1 sample should be stored in the FIFO in every RAC, right?
So the write pointer should advance by 1 in every RAC, right?
But FIFO_RDY on wave form seems like a moving that I can’t understand.
Thanks.
Takayuki.
