Other Parts Discussed in Thread: AFE58JD48, AFE5808A
We are using the EVM with a COTS FPGA board. They I/F using a custom cable we've made, for LVDS transmissions and the cable works as it was 1st tested with the AFE58JD48-EVM.
In the GUI, I set the clock source to single ( and board jumpers too ), lastly the ramp pattern was selected ( I know the board settings don't matter for such a setting, but just to say what I've delta'ed ). From our work with using the 16-ch EVM, we know that the cable and FPGA bit file are good, for ramp and actual analog inputs, going to the FPGA. But in Vivado Lab Edition, the iLA values are either zero or 0xFFFF, instead of ramp pattern. We don't want to try analog inputs until we do ramp ( and are sure of how to operate the GUI ).