What is the input bandwidth for the differential clock inputs (CLK+/CLK-)?
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What is the input bandwidth for the differential clock inputs (CLK+/CLK-)?
Hi john,
The ADC12QJ1600-SP supports clock rates up to 1.6GHz.
Best,
Eric Kleckner
Hi Eric,
The question was more to do with the analog input bandwidth of the clock input and not the supported clock rates.
Hi John,
The clocking inputs do support very high bandwidth, do to the high amount of slew required on he 1.6GHz sampling edge. So at least 2GHz or more would be a good guess. We can reach out to the design team to see if there are any simulation numbers to help back this up.
Is there an underlying question about the clock?
Regards,
Rob
Hi Rob,
It's more a question of how to set the upper integration limit for the input clock jitter (reference TI app note TIDU870). This will also tie into any bandpass filtering we put on the 1.6GHz input clock to suppress harmonics of the input clock.
Thanks!
John
Hi John,
Understood. Typically you can use the Nyquist or Fs/2 to set the integration BW. Most of the noise will always be considered wideband noise, its the biggest contributor, when you additive accumulation and you will be at the floor of the device well before this point for sure.
Clock filtering is always a good idea, however, most customer don't, so kudos to you!, this will also help keep anything out of the clock inputs in general and not let any unwanted noise or spurious convolve to the output spectrum. Just keep in mind, some filters can hamper the clocks slew rate, so you may need to put a gain stage before the filter to keep the slew maximized, while filtering. May need to iterate this a bit on the lab bench to get the setup just right.
Regards,
Rob
Thanks Rob! That answers my question.
Understood about clock input slew rate vs. filter.
Regards,
John