DDC112: Regards DVALID pin response

Hello Sir,

In my design, the DDC112 IC is controlled by a Controller.  Using Timer, the pulse is generated for CCLK and Conv pin and its frequency is 10MHz and 1KHz respectively. DCLK, Dout, DIN, and DXMIT pins are controlled by SPI Peripheral. In this design DVALID pin is connected to Micro controller pin, Micro controller should not read frequently the status of the DVALID pin. Only read the DVALID pin status at specific ADC data read function.

In that case, the DVALID pin goes low after 1st integration completion but the DXMIT pin does not make it low, after a few integration period completion only the Microcontroller enters the specific read function and this function DVALID pin status is read.

Note: This information get from design Support forum, "DVALID is low when the data is ready to be read out. If the data does not get read out, DVALID needs to go high again briefly before dropping low to show that the data is once again ready. The figures in the datasheet assume that data is getting read out soon after DVALID goes low which causes DVALID to go high again when DXMIT is pulled low and DCLK is toggled to read out data."

My doubt is,  What will happen if the DXMIT pin does not make low after the DVALID pin becomes low( at data is a valid condition in the ADC) for a few integration time period? It means Data from ADC is not read for a few integration periods and then What will be the status of the DXMIT pin in this period? Give me the solution for DXMIT making high while data is not reading from ADC for a  few integration periods.

Thanks & Regards,
Gowtham