Part Number: ADC12DJ5200RF
I have
We are using x3 ADC12DJ5200 ADC ICs in my design, We have Phase matching requirement among the 3 ADCs. Below listed are the considered and implemented.
- All x3 ADC sysref signals and x3 FPGA Sysref Signals are length matched.
- All x3 ADC device clocks are length matched.
- All x3 FPGA device clocks are length matched.
I have few query on length matching of Device clock to Sysref clocks. I understood for one ADC IC there is no need to match the Device clock and sysref (same is followed in adc Eval Board) and also mentioned in the Forum.
But in my board, I have multiple ADCs and need phase matching. for that everywhere it is mentioned that Device clock and sysref signals to be length matched.
As Sysref is generating from LMK IC and device clock is generating from the LMX Device (LMK Device clock length is the combination of LMK Output to LMX Input trace length, LMX IC delay and then LMX Out to ADC device clock input trace length) similarly as did in Eval board.
So can you please specify how to consider the length matching for these signals? Means which path of device clock I should consider?
Regarding JESD204B lines, JESD204B Each channel consists of x8 lanes. What can be the maximum tolerance allowed within one channel?
To achieve phase synchronization between X3 ADC ICS then what is the maximum trace length difference allowed across all the 48 Channels?
In my design, I have 3 ADCs, we have phase matching requirements. So Do we need to need the length match for x48 JESD204B Lines?
Please suggest us the requirements of JESD204B Lanes length matching.
