TLA2528: Reading A/D inputs

Hi Ken,

Welcome to our e2e forum!  Can you attach a better schematic?  What you have posted is fuzzy and hard to read.  I don't necessarily see anything wrong with your setup/initialization sequence.  Are you looking at he OSR_DONE bit in the SYSTEM_STATUS register?  Do you have details on the expected conversion result versus what you are actually getting in return?

Hi Tom - Thanks for the quick reply.  Sorry about the schematic but it is the best I have at this time.

Regarding issue 2: I think the problem is it looks like there is a diode clamp on the open drain output to the AVDD supply.  In my design I have both AVDD and DVDD connected to the 3.3 volt supply.  I was under the assumption from figure 48 in the data sheet that I could pullup the open drain output to 5.5V max but I think that is only if the AVDD supply is connected to 5V source.  In my case where AVDD is connected to a 3.3 V supply it looks like the output is clamped to 0.4V above the AVDD supply.  I think this is what is limiting my open drain output (but not positive).

Regarding issue 1: Is there a command I have to send to start an A/D conversion?

For testing purpose I connected a 3.0 volt source to one of the analog inputs.  AVDD is at 3.3 volts so 1 LSB should equal 805.7uV.  For a 3 volt input I think the output should be around 1241 counts per volt so I was expecting to see a value of 3 x 1241 = 3723.  This would be around E8B hex after shifting out the 4LSBs.  I think this is what I should have read back?

I am just trying to do a single input A/D conversion read just to see how the A/D inputs work.

Thanks again for your help

ken

Hi Ken,

For the GPIO, the voltage is limited to AVDD plus 300mV, so your clamp diode theory is correct.  Reading a single channel would be like Figure 26 and just keep writing the same Channel ID.  Can you grab a screen shot of your I2C communication lines?

Hi Tom- Regarding the A/D read issue we continuously read back data of FFF2 hex.  The 2 is the channel ID.  For our input we expected to read back something close to DF32, again the 2 is the channel ID.  Also when we check the system status register we read back 81 hex.  I expected to read back 88 hex.

Do we need to write to the BOR bit in the system status register after a power on to clear this bit?

Yes, you do need to write to the BOR to clear the flag.

Hi Tom- I found a missing trace on the PCB going to channel 2 of the A/D input so that was why we were reading FFF2 all the time.  I added a jumper wire in place of this trace and it seems to be reading data now that changes when we change the input.  Can you confirm that if an A/D input is floating one would expect to see FFF  on a read?

I got as few more questions on the operation of this part.

1.  Can you briefly explain what the calibration routine does when we write a "1" to bit 1 of the GENERAL_CFG register?

2. Does this calibration work on only one channel (if so how do we select which channel?) or does it work on all channels at once? When we set this bit to a "1" and immediately read it back it is always a "0" indicating calibration is complete.

3. When we put the same input into a few channels we get output data that varies by as much as 3/4 of a volt.  Since we don't need high speed data acquisition (read A/Ds once every 5 seconds as they are just providing feedback on DC power supplies) can you recommend OSR_CFG register setting, OPMODE_CFG register setting that might improve the accuracy?  I think using averaging mode would greatly improve the readings?

4.  In our trouble shooting we were playing around reading the test pattern from the A/D channels by writing a 90 hex to the DATA_CFG register (output fix pattern and append data with channel ID).  When we read back the data we noticed the 1st read of channel 0 gave us the correct result but the next reads of the other channels seems to have the correct data but the channel ID data was incorrect.  Is there something we have to do in between consecutive channel reads to fix this?

Thanks for your help.

ken 

The old missing trace trick!  I hate when that happens!  To your questions:

1. Internally, the input to the ADC is shorted to ground and a conversion is done.  The resulting offset value is then added to or subtracted from future conversion results.
2. The calibration works on the ADC itself, so it impacts all channels.
3. The analog inputs in your case may need to be buffered.  Setting the OPMODE_CFG to 0x10 and enabling averaging should help as well.
4.  Are you getting the same 0xA5A?  I don't think the CHIDs are included with the test pattern, which is why CH0 was 'correct'.  When you run in normal operation, do the CHIDs come out as expected?

Tom can you confirm the process for doing averaging is as follows:

1. Set OSR_CFG register for number of samples to be average.

2. Initiate conversion by setting bit 3 in GENERAL_CFG register

3. Check for conversion complete by reading bit 3 (OSR_DONE) in SYSTEM_STATUS register

4. Read data (output is 16 bits)

Thanks

ken

Hi Ken,

Yes, that is correct.

Hi Tom - I got a related question regarding this part.  After power on / initialization we perform the ADC Offset Calibration by setting the cal bit in the General_CFG register.  After setting this bit to a 1 we immediately poll this bit and see that it is 0 which indicates the calibration is complete.  We never can capture this bit as a 1 indicating calibration is in progress.  I then set one of the analog inputs to ground and we are reading a value of about 162 decimal from this channel.  I expect the value to be around 0 +/- a few LSBs.  As I increase the input values it seems like the decimal value read has an offset that increases with input voltage.

We currently have the averaging filter enabled with the OSR_CFG register set for 128 samples to be average thinking this would average out any noise in the system.

We even tried doing multiple A/D reads from this channel with a 1 second pause between reads and still experience this offset.  We also see this same offset behavior on other A/D channels in this part.

Can you offer any advise to help us trouble shoot this A/D offset we are experiencing?  Could we not be executing the Offset calibration correctly? 

Thanks

ken

Hi Ken,

Can you provide a more comprehensive schematic?  Do you have buffers driving the ADC inputs?

The ADC inputs are coming from a TEC controller.  The data sheet of the TEC controller says these signals are buffered outputs with 1K ohm output impedance.  I don't have a schematic of the the internals of this part. I have measured the ADC inputs with a DVM and when the signal is supposed to be 0 volts it measures 0 volts on the DVM. 

Hi Ken,

Can you probe the input(s) with an oscilloscope while the converter is running?  I'm curious to know/see if there is any disturbance at the time of sampling the ADC input.