ADS6445 /ADC to FMC Rev C adapter / Spartan 6 DSP LX150T

Hi,

Let me try to take some of these questions in a different order, starting with the ADC and moving over to the adapter board and then to the developemnt platform, seeing if this might help.

You will need to be come familiar with the 1-wire and 2-wire data formats described in this data sheet.  In 1-wire mode, the sample data is presented on a single LVDS differential data line one bit at a time until all 12 bits (or 14 or 16 depending on device and mode) are transmitted.  In 12 bit mode, this means that the data rate of the bits must be 12x that of the sample clock in order to get all 12 bits out during the sample period.  The data 'channel' is LVDS, which is differential in nature so there is a 'P' side and an 'N' side that are always to be inverses of each other.  In 12bit seriaization 1-wire mode, the clock that goes with the data need only be 6x that of the sample clock since we can use both rising and falling edges of this bit clock to register the data into the FPGA.  And finally there is also a frame clock that is needed to identify where the sample boundary is on the serialized data.  The frame clock can be though of as an extra data pair that happens to have a known and fixed data value each sample, so that you can look at the place where frame clock goes from low to high and know that on the data pair also this is the place where bits from one sample finishes up and the bits for the next sample start.

One drawback of 1-wire serial mode is that the speed of the LVDS data limits the sample rate that you can process.  For example, in 16bit mode at 125Msps, this would mean 16 x 125M = 2Gbps on the LVDS data pair.  That is too fast for an FPGA LVDS input.  So we offer the option of serializing half the bits on one LVDS data pair and the other half of the bits on another LVDS data pair.  This doubles the number of LVDS data pairs needed but cuts the data rate required down by half.  So yes, DA0_M and DA0_P refer to the data for one of the wires for channel A, and DA1_M adn DA1_P refers to the other wire for channel A if 2-wire mode is employed.  Regardless of how many chanels or 1-wire or 2-wire mode, only one bit clock is needed for all the LVDS data pairs and frame clock, and only one frame clock is needed to identify the sample boundary on all data pairs.

So you would need to trace out on the EVM the connector assignments for all the LVDS data pairs, which you have.   The LVDS pairs for channel A go to certain pin assignments on the connector and the schematic in the EVM User's Guide calls out the assignments.  The FMC adapter card also has a routing assignment to get the LVDS data pairs over to the FMC connector, and you also know how to trace this out.  So now you know which signals are getting to the development platform and on which FMC connector pins. 

Regarding the SPI port, this is a simple 3-wire control bus that lets you write into the register space of the ADC to set certain modes of operation.  The EVM is configured by default to *not* use the SPI signals for this purpose, but rather to let the jumpers on the EVM choose the more common modes of operation.  To change the EVM over to let the FPGA drive the SPI, *four* surface mount 0-ohm resistors must be moved.  The RESET signal must be moved from being tied high to the other position.  The signals SCLK, SDATA, SEN must have their resistors moved from conneecting to the 4-position jumpers to connecting to the connector to the FPGA.   Then the TSW1200 or your developement platform can drive the SPI signals.

The TSW1200 User Interface GUI has an option under the 'TEST' selection to choose the SPI Setup test.   (If you are using version 2.0 or newer of the TSW1200 GUI)  In this window you can enter the address of a SPI register and the value of the data you want to write to that address, and add that to a queue of register accesses.  Then when you press Send Data all of the register accesses in the queue are sent to the FPGA which in turn controls the SPI access to the data converter on the EVM by bringing SEN low and then bringing SCLK low then high or high then low for each bit of addess and data on the SDATA line.  Then bringing SEN back high after each register write.

The posting you quoted towards the end there was in relation to how the frame clock is to be used.  And because of this frame clock, we had to revise the bridge card and come out with a new revision of the circuit board.  (We are currently up to revision C)  The first revision of the adapter routed the frame clock to a pin on the FMC connector that connected to a clock input on the FPGA.  But earlier in this posting I mentioned that the frame clock can be thought of as another data pair that has a known data pattern.  And in fact the frame clock is to be latched into the FPGA using the bit clock just like it was any other data input.  So for revision C we moved frame clock to an FMC pair that goes to just another data input, not a global clock input.

Regards,

Richard P.

Hi Richard,

Just some followup/additional questions,

When you put the ADC into sync mode sclk(low) sdata(high) and a sync pattern is output on all channels that means all 8 pairs, right?  From DA0_M/P, DA1_M/P ....DD1_M/P?  But is a sync signal generated on DCLK and FCLK pairs as well or must i set those up as per your above post?

For the sync signal is there a default pattern built in or must it be set on first run, and if it is built in, can it be changed to a new default or does it need to be set each time you run it after a power down?

Lastly, again from the ADS6445 documentation, p25 shows the RGC package pinouts for 2-wire config, and p28 for pinouts of the 1-wire config.  In the 1-wire config the need for half the channel pairscreated 4 pairs of UNUSED pins and shifted the position of the remaining channel input pairs.  Does this affect the pinouts for the Samtec connector as well from slau195 p25 ads64xx user guide where it shows all 8 channel pairs?  Are the pinouts accurate for 1 wire and if not do you have the proper pinouts for 1 wire for the Samtec connector.

Justin

Regarding the SPI port, this is a simple 3-wire control bus that lets you write into the register space of the ADC to set certain modes of operation.  The EVM is configured by default to *not* use the SPI signals for this purpose, but rather to let the jumpers on the EVM choose the more common modes of operation.  To change the EVM over to let the FPGA drive the SPI, *four* surface mount 0-ohm resistors must be moved.  The RESET signal must be moved from being tied high to the other position.  The signals SCLK, SDATA, SEN must have their resistors moved from conneecting to the 4-position jumpers to connecting to the connector to the FPGA.   Then the TSW1200 or your developement platform can drive the SPI signals.

Unless I'm missing something my EVM version doesn't have these 0 ohm resistors, for J6 and J8.

So you're saying I need to move the 0 ohm resistor on J5 from  position 2-3 to position 1-2 and put 0ohms in the 1-2 position for J6 and J8 as well.  but the thing you said about the reset i'm not sure about.  Are you saying that J7 must have the resistor moved from 2-3 to 1-2? if so doesn't that mean I can't use Parallel outputs?

Hi,

i think you may be right that two of those jumper positions may not have a resistor at all in the default condition - if by leaving the position open circuit means that the ADC itself does not use these pins for parallel configuration.  Ah yes, SCLK (J6) and SDATA (J8) when pulled both low = normal operation and there are pull down resistors for these pins on the board.  So yes, you would have to add the 0-ohm resistors to these positions.

For reset, yes J7 must have the resistor moved to position 1-2.   By Parallel configuration, this means simply that a number of pins are used for configuring the device rather than using three serial pins to configure the internal registers.  This has nothing to do with the sample outputs, which are on a parallel bus of pins that each have sample data serialized out on them.

Regards,

Richard P.