• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 755 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1278 Clock Requirements (acceptable jitter)

Jonathan Horne
Prodigy 20 points
Other Parts Discussed in Thread: ADS1278

Can someone offer guidance on clock requirements for the ADS1278 24-bit sigma-delta ADC?

We'd like to optimize SNR performance for a relatively low frequency input signal (~4kHz). We plan to clock the device at roughly 4MHz in high resolution mode. I am trying to specify a VCXO to use as the source and don't know how tight phase noise and jitter specs need to be. The data sheet simply suggests a low-jitter crystal.

There appears to be a ton of literature on clocking requirements for high speed converters, but the sigma-delta information is somewhat more scarce.

Any suggestions or pointers to related documentation would be greatly appreciated.


Thanks, Jonathan

 

 

  • 0
    TI__Guru**** 181771 points

    Hi Jonathan,

    Welcome!  Thank you for asking about the ADS1278 clock jitter requirements!  Take a look at the attached spread sheet and see if it answers some of your questions.  The 'high speed' converters use (for the most part) a pipeline architecture where jitter plays a much bigger role in performance.  Since the ADS1278 is a Delta-Sigma, you don't need as tight a control on your clock jitter to maintain good SNR performance. 

    ADS1278 CLK jitter analysis.xls
  • 0 in reply to Tom Hendrick
    Prodigy 20 points

    Hi Tom,

    Thank you very much for the spreadsheet. It’s great to get some analysis for the Sigma-Delta. Is there a reference from which this is derived?


    The equation for DR_CLKJIT looks very familiar. For pipeline converters, one often sees:

       SNR = 20*log [ 1/ (2*pi*fin*tj) ]

    Where tj is the combined clock and aperture jitter. I believe this is the same as your delta_t.

     For example, see SNR derived here (equation 2.34)

    http://www.analog.com/library/analogDialogue/archives/39-06/Chapter%202%20Sampled%20Data%20Systems%20F.pdf

     

    Taking the reciprocal gives the same as your DR_CLKJIT equation with the exception of the 2*OSR factor.

     For a pipeline converter, we normally use

        delta_SNR = 10*log(OSR).

     Again, this looks very close to what you have. The only difference is the factor of 2. Is this somehow related to the sigma-delta architecture?

     

    So a couple of questions:

    • It would be great to see a derivation of the DR_CLKJIT equation in your spreadsheet. In particular, I do not know the origin of the 2x factor. Nonetheless, if the numbers are right, I see that you’re correct in saying that clock jitter will not be a problem with the sigma-delta.
    • The bigger question: is this standard over-sampling analysis valid for jitter-induced SNR in a Sigma-Delta? If so, it would seems there’s no real difference between the different ADC architectures (pipeline, sigma-delta, etc.) in the SNR performance analysis.

    Thanks again for your spreadsheet and for your assistance,

    Jonathan