ADC32RF45 EVM SETTING

CIOU YuAn

Prodigy 75 points

Other Parts Discussed in Thread: LMK04828, ADC32RF45

Hi :

PIC1 is setting that i uesd to my design.

i used onboard clock.

PIC2 is output signal form LMK04828 Which output clock to FPGA and ADC32RF45.

My question is PIC3 LMK04828 output state that all the LED should be turn on?

If the only PLL2_LOCKED's LED turns on . is it correct?

pic1 :

pic2 :

pic3 :

over 2 years ago

0 Chase W over 2 years ago

TI__Mastermind 23990 points

Hi CIOU YuAn,

If the optional 10MHz signal is not applied, PLL1/LMK LOCK will not appear. Since you are only using PLL2 in this case, this led will be the only one to light. The other two LED are for general purpose outputs through the CLKin_sel 0/1 pins of the LMK. You can see the LMK04828 datasheet for options, such as PLL digital lock detect, etc.

Regards, Chase

0 CIOU YuAn over 2 years ago in reply to Chase W

Prodigy 75 points

Hi Sir :

What do i know the ADC32RF45 EVM serdes pll locked?

I make ADC32RF45 EVM and KCU105 EVM connected . and i can't see the FPGA's rx_jesd204 rx_tvalid signal turn on.

Is there a sequence between ADC32RF45 EVM and KCU105 EVM? (power on , after downloaded file)

0 Chase W over 2 years ago in reply to CIOU YuAn

TI__Mastermind 23990 points

Hi CIOU YuAn,

If the device is operating at 1536MSPS and in LMFS:8-2-8-20, the serdes rate will be 1536M*4 (fserdes/fclk ratio from Table 14. JESD Mode Options: Bypass Mode). The ADC itself does not have any lock flags or status. This will have to be checked using the clocking wizard of the KCU105. I think there will be some output status options such as PLL lock or PLL locked status but you will have to check this with xilinx as I am not sure how to do this.

Regards, Chase

0 Chase W over 2 years ago in reply to Chase W

TI__Mastermind 23990 points

Since Xilinx uses 32-bit data bus, I believe the reference clock for the transceiver pll should be serdes/80, which in this case will be 1536M*4/80=6.144Gbps/80=76.8MHz.