ADS7056: ADS7056

Hi Tom,

Thanks for your prompt response. From Section 8.4.1 I read "The device enters ACQ state at power-up, at the end of every conversion, and after completing the offset calibration". Based on your response and the datasheet I then understand that with no external activities and with /CS kept high the ADS7056 performs one acquisition at power up and then goes IDLE. Data from that acquisition kept in a buffer(?) until the host (FPGA) lowers the /CS. When /CS goes low data from initial acquisition is outputted. Is that correct?

I also have another question. In 8.4.2 it stated that the ACQ state starts when the 18th SCLK falling edge is received regardless of the /CS. Then, how would I be able to perform an "offset calibration during normal operation" (8.4.2)? It seems that I am missing something or the diagram in Fig 42 doesn't apply .

Thanks

Marco

Hi Marco,

Not completely correct - when the ADS7056 is in acquisition mode, it just means that the analog input is applied to the internal sample and hold cap.  When /CS is applied, the sample and hold disconnects from the input and whatever voltage was captured is converted once the SCLK is applied.   The SDO outputs zeros on the first application of /CS while the SCLK converts the first acquisition.  The next cycle presents the first conversion result while the second conversion is taking place.

For offset calibration, did you notice the '64 SCLKS' comment in 8.4.3.2?  It's the extra clock cycles that do the offset calibration function.

Hi Tom,

I am afraid I don't follow.

a) I understand that if we are in the ACQ state the analog input is applied to the sample and hold cap (Figure 36 or 44). So, my question (related to the very first one) is the following: what is the state of the ADS7056 after the very first acquisition (from power up) is over and no falling edges of /CS are received after that? According to Fig 39, the ADS7056 stays in the ACQ state.

b) Therefore the switch is still closed and the analog input is still connected to the sample and hold cap. Then, if I change the analog input, the ADS7056 should be now sampling the new input. Is that correct?

c) If so, at the next /CS falling edge and at every SCLK rising edge after the first falling I should see SDO data consistent with the new input (and not the old one). This is not what I see. What am I missing? Probably my understanding in a) or b) incorrect

For the offset calibration I did the need of 64 SCLKS. Let me rephrase the question: what is the ADS7067 state between the 18th SCLK falling edge and the 64th one? From 8.4.2 it seems to be ACQ state

I apologize if it is taking me a bit longer to understand

Thanks

Marco

Hi Marco,

From power up, the device is in its acquisition mode - if /CS is held high and you switch your input, you are still in acquisition mode and the new 'channel' is going to be sampled  Maybe the fact that there is no MAX time for the acquisition phase is your confusion point?  The part will stay in ACQ mode until the /CS is applied.  If you power up, don't apply /CS or SCLK, but change the analog input, you sample the new analog input.

Lets call the acquisition from powerup sample A.  With the first application of /CS and SCLK, SDO provides 0x000 while sample A is converted and it will be presented to SDO during the next conversion cycle (A+1).  SDO is always from the conversion that happened in the previous cycle.

For the CAL function, holding /CS low and applying the addition clocks puts the device into an internal acquisition mode which essentially shorts the ADC input to ground, does a conversion, and lodes that conversion result to an internal register.  That internal offset is then applied to all subsequent conversion results.

Hi Tom.

The MAX time is not the confusing point at all. From the get go I would expected that the ADS7056 keeps sampling whatever analog input is connected to until the first application of /CS (which by that I think you mean falling edge of /CS). But I do not see that (see bullet b) and c) above).

I understand your example but I don't think that applies to me. So, let me ask again the same question but in a more pedantic way.

1) At power up the ADC is connected to a ~0V analog input and /CS is held high. After few minutes I send the first /CS falling edge and 18th rising/falling SCLK edges: what am I expected to see on SDO?

2) /CS is now kept high. I change the analog input to ~3V. I send the second /CS falling edge and 18th rising/falling SCLK edges: what am I expected to see on SDO? Is the output consistent with 0V or 3V?

I would appreciate itemized answers on 1) and 2). That way we can resolve the issue and I can probably debug the issue elsewhere (firmware or software)

Ok, I understand the CAL and this is what I am implemented in the VHDL. However, I am still convinced that the text is confusing.

Thanks

Best,

Marco

Hi Marco,

1. See the second paragraph of section 8.4.2.  The first serial transfer frame is your application of /CS and 18 SCLKs.  You should get zeros out of the SDO pin.  That is an internally forced condition, not an actual conversion result.
2. The initial 0V source that was present before the first application of /CS was converted in 'the first serial frame' and that conversion result is being presented to SDO while the ~3V sample is being converted.  The conversion results from the 3V source will be presented in the next serial transfer frame.

Let me know if the process is still not clear.  Figure 40 shows 'Sample A' on falling /CS and 'Sample A+1' on the next falling /CS.  Note that SDO shows output data for 'Sample A-1'.