ADS1278: ADS1278 Testing

Hello Tex,

Can you provide a schematic of your breakout board?  Also, please let me know how the device is configured, SPI or Frame Sync.

For expected timing, please look at the SPI Format Timing diagram section of the datasheet.  In SPI mode, CLK, SCLK, and DIN are all ADC inputs, and /DRDY and DOUT are outputs.

Regards,
Keith Nicholas
Precision ADC Applications

Hi Nicholas,

i don't have the schematic right now but it is connected to the same pins of ADS1278.. 

i haven't went to the programming part for data processing actually but i just generated sclk from the controller and gave required inputs to the IC 

reviewed SPI format timing diagram and gave inputs as u can see in the image,

The output in the scope are,

Dout 200Hz, DRDY 200Hz & SYNC 200Hz 

drdy should go low and high for every 24 bits as per my understanding

Please tell me what mistake am i doing right now 

Best regards,

Tex

Hi Tex,

This a holiday week in the US, we will respond to you next week. Thanks for your patience

-Bryan

Hello Tex,

The FPGA needs to monitor the /DRDY output from the ADS1278.  When /DRDY transitions from high to low, data are ready to be read from the ADC.  

CLK needs to be a continuous signal; the SCLK will idle in the low state.  When /DRDY goes low, the FPGA will then generate 24 SCLKs, and the 24b conversion result will be on the DOUT pin.

When using SPI, the most common configuration is TDM mode, where all ADC channels are shifted out on the DOUT1 pin.  In this case, the total number of SCLKs will be 8*24=192 for each SPI frame.  The FORMAT pins need to be connected to ground to support this mode.

Here is the order of operation.

1. Monitor the /DRDY pin, wait for /DRDY to go from high to low.

2.  Send 192 SCLKs, read data on DOUT1 pin.

3.  After data has been read, wait for the next /DRDY transition from high to low.

Assuming CLK=27MHz, SCLK can also be set to 27MHz.  This will support data rates up to 105468 sps.

The SYNC pin should be held high under normal use.  The SYNC pin functions as an ADC reset and should only be used to re-synchronize the ADC after power-up and after any mode change.

I will need to see a sketch showing all pin connections of the ADS1278 to further help.  Also, a waveform plot showing the CLK, SCLK, /DRDY and DOUT1 signals, will also help.

Regards,
Keith

Hi keith,

I'm using 001 Fixed tdm SPI format,

i'm trying to get 200 samples in 1 hz sine wave,

as u said drdy signal should go high to low 24 clk cycles 

Both DRDY and Dout showing same output..

My connections are.. for 200 samples

sclk: 102400, clk: 102400, vdd: 3.3V

Please tell me what are all the mistakes am i doing..

Best regards,

Tex