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ADS8341 acquisition time internal clock mode

Ian Gregg
Prodigy 180 points

Other Parts Discussed in Thread: ADS8341

Data sheet specs say min 4.5 clk cycles, internal clock freq 2.4 MHz.  But timing diagram, figure 6 shows acquisition time as 4 cycles of DCLK which is a lot slower in my case.  Which is it?  Trying to design the input RC filter based on this paper: Designing SAR ADC drive circuitry

  • 0
    TI__Guru**** 182881 points

    Hi Ian,

    Welcome to the Precision Data Converter Forum!  The ADS8341 sample time is based on your applied DCLK.  The electrical characteristics tables give an External Clock Frequency range of 24kHz to 2.4MHz so you have a sample time ranging from 187.5us to 1.875us.  The internal 2.4MHz clock is only used for the conversion process.

  • 0 in reply to Tom Hendrick
    Prodigy 180 points

    Ok, getting somewhere now.  I have slowed my SPI write down as much as I can to 62.5 kHz to maximise the acquisition time.  Waiting for BUSY then reading the data at 2 MHz.  Have put a 4k7 - 1nF RC filter on the input of the ADS8341.  Sampling at 1 kHz, averaging ten samples at a time and stepping a source in small steps 10 times per second gives me the result below.  This is probably good enough for my application but I would like to know the potential source of the glitches that remain and some ideas to eliminate them.

  • 0 in reply to Ian Gregg
    TI__Guru**** 182881 points

    Hi Ian,

    What does the y-axis scale represent?  Is that individual codes, or perhaps millivolts of input to the ADC? 

  • 0 in reply to Tom Hendrick
    Prodigy 180 points

    Tom

    I did trim off a multiplier for the Y axis, it should say x 10^3.  As I said, this is the accumulation of 10 readings and is zoomed around mid scale so 327680 is half of full scale or 327.68 on the graph I attached.  Sampling at 1 kHz and accumulating 10 samples gives an output update rate of 100 per second.  The input was a programmed linear series of small steps from a calibrated instrument at 10 per second.

  • 0 in reply to Ian Gregg
    TI__Guru**** 182881 points

    Thank you for the clarification Ian,

    Depending on how you have the ADS8341 set up, you may be reaching the limits of it's capabilities.  That large glitch in data at (about) mid scale may be the INL/DNL kicking in at a major code change.  It may also be caused by a shift in voltage potential due to layout and/or grounding.  If you'd like to post your schematics and/or layout, we'd be happy to review them for you.  If you rather not post them here, we might be able to have a chat off line.

  • 0 in reply to Tom Hendrick
    Prodigy 180 points

    Tom

    Thanks for the offer but layout could definitely be an issue as this is a prototype that has been modified/hacked quite a bit.  It will be interesting to see if the situation improves with the next iteration with a nice clean layout.  It is good enough for my application as it is now.