Part Number: ADC09QJ1300
Hi team,
Here is a question one of our customers is experiencing, could you please provide some troubleshooting suggestions?
I was debugging the ADC09QJ1300 and found that the link was unstable, the AD was configured with a sample rate of 600M, 4lane mode, 7.425G lane rate, send prbs31 to the FPGA, the FPGA's ibert detection signal error rate and eye diagram.
1. Hardware connection
The AD9517 clock chip produces two 150MHz clocks, LVPECL levels, one clock for ADC clk+/- and another clock for MGTHREFCLK+/- for FPGA -zu4ev. The D0+/-~D3+/- total of 4 differential pairs of AD are connected to the gth port rx of the FPGA.
2. AD Configuration
AD input clock 150MHz, cpll passed to produce a 600MHz sample clock. JESD configured for JMODE8 mode, 66/64b encoding, 4lane output, line rate 600MHz X12bit X 66/64=7.425Gbps, prbs31 sent, configuration register as follows
send_buf[0]=0x00;
send_buf[1]=0x00;
send_buf[2]=0xb0;//复位
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
while(recv_buf[2]!=0x01)
{
send_buf[0]=0x82;
send_buf[1]=0x70;
send_buf[2]=0x00;//等待初始化完成
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
}
send_buf[0]=0x00;
send_buf[1]=0x58;
send_buf[2]=0x81;//spi控制，PLL使能
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x02;
send_buf[1]=0x00;
send_buf[2]=0x00;//先关闭JESD
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x61;
send_buf[2]=0x00;//CAL_EN关闭
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x02;
send_buf[1]=0x01;
send_buf[2]=0x08;//配置JMODE 8
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x29;
send_buf[2]=0xb6;//开启sys_ref
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x29;
send_buf[2]=0xF6;//开启sys_ref 配置sysfre_window
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x2a;
send_buf[2]=0x00;//配置LVPECL
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x30;
send_buf[2]=0x00;//配置模拟信号Vpp采样最大值
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x31;
send_buf[2]=0xA0;//配置模拟信号Vpp采样最大值
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x5c;
send_buf[2]=0x01;//CPLL_RESET
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x3f;
send_buf[2]=0x4a;// CPLL_VCOCTRL1
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x3d;
send_buf[2]=0x0a;//0x06;//CPLL_FBDIV1
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x3e;
send_buf[2]=0x04;//0x08;//CPLL_FBDIV2
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x5d;
send_buf[2]=0x41;//VCO_CAL_CTRL
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x5c;
send_buf[2]=0x00;//CPLL_RESET 释放
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x48;
send_buf[2]=0x08;//预加重
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x02;
send_buf[1]=0x02;
send_buf[2]=0xff;//KM1 Register
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x02;
send_buf[1]=0x05;
send_buf[2]=0x0e;//测试模式选择 发送prbs31
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x61;
send_buf[2]=0x01;//CAL_EN
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x02;
send_buf[1]=0x00;
send_buf[2]=0x01;//打开JESD
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x6c;
send_buf[2]=0x00;//打开CAL_SOFT_TRIG
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x6c;
send_buf[2]=0x01;//打开CAL_SOFT_TRIG
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
u8 result;
u32 addr=0x10000;
u32 wr_data;
u32 rd_data;
while(1)
{
send_buf[0]=0x82;
send_buf[1]=0x08;
send_buf[2]=0x00;//
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
result=recv_buf[2];
if((result & 0x44)!=0x44)//判断link up是否成功
{
i=0;
while(i==0);
}
}
3.FPGA Configuration
ibert has an input clock of 150MHz, 4lane rx, set line rate of 7.425G to see the communication quality between AD and FPGA.
4. The phenomenon is as follows
Unstable link building. By reading the 0x208 register of AD, the LINK_UP and SPLL_LOCKED bits are unstable , sometimes 1 and sometimes 0. What may be the cause of the above phenomenon? Any troubleshooting ideas are appreciated.
Best Regards,
Amy
