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DAC3482: Clock Distribution Review and A Question Related to FIFO Out Clock

Alperen Berber
Prodigy 10 points
Part Number: DAC3482

Hello,

I want to run my DACCLK at 524.288 MHz with an interpolation factor of 16x. The PLL will be configured so that it converts DACCLKP(N) of frequency 32.768 MHz to the given DACCLK. The PLL configurations are given below:

Prescaler = 7,

VCO @ 3.670016 GHz,

Coarse-tuning bits = 38,

M = 32, 

N = 2. 

Firstly, I wonder whether this configuration is consistent or not. I'd be glad if you review it.

Secondly, and more importantly, I have an issue related to FIFO Out Clock. DATACLK that I will provide will be of frequency 32.768 MHz, which is same as that of DACCLKP(N). As far as I could understand, the clock rates at both sides of the FIFO should be equal (i.e., DATACLK and FIFO Out Clock should have the same rate). Since I am going to use my DAC at word wide mode, I am reffering to the the formula FIFO Out Clock = DACCLK/(2*Interpolation Factor) at page 31 of the datasheet. In this case, an ambiguity occurs: DATACLK and FIFO Out Clock have different rates (DATACLK = 32.768 MHz, FIFO Out Clock = 16.384 MHz). Why is there such an ambiguity? Is it because the FIFO reading data at both edges of FIFO Out Clock? Or, is there no such a thing and I'm missing a point? I'de again be glad if you can help me on this issue.

Thanks.

  • 0
    TI__Expert 3450 points

    Hey Alperen, 

    Your PLL settings all look correct to me, with the exception of the coarse-tuning bits. I am calculating a value of 36, not 38. Per the equation listed in Figure 57 on page 36 of the datasheet coarse-tuning bits ~= (VCO_frequency - 3253)/11.6 = (3670.016 - 3253)/11.6 = 35.95. 

    For your second point, You will want to run the DATA clock at 16.384MHz and not 32.768MHz. The reason is because I and Q samples are provided on the rising and falling edge of the dataclock respectively. 

  • 0 in reply to Matthew Kramer
    TI__Expert 3450 points

    On second glance the I data is on the rising edge and Q data is on the falling edge of the DATACLK, and therefore FIFO clock should be DACCLK/interpolation from my understanding (which is the same as what you stated). Let me ask around a bit and see if I can get some clarification on this. 

    Regards, 

    matt

  • 0 in reply to Matthew Kramer
    Prodigy 10 points

    Thanks for the feedback related to PLL settings. I corrected the coarse-tuning bits on my configuration. If you excuse me, I have an additional question related to the PLL settings. In the datasheet, dual charge pump is being advised when overall divide ratio is greater than 120. However, there is no advice on the choice of pump charge setting when the loop stability is internally guarranteed (when overall divide ratio < 120). What would be your advice on the choice of pump charge settting in this case?  

    For the second question, I am looking forward to see the results of your inquiry as I am just in the same standpoint as yours in the second answer.

    Thank you so much.

  • 0 in reply to Matthew Kramer
    Prodigy 10 points

    Hi Matthew, is there any news about your research?

  • +1
    TI__Expert 3450 points

    Hey Alperen, 

    In word mode, you should run the data clock at the DACCLK rate / interpolation (32.768MHz in your case). The channel A data will be strobe on the rising edge of the clock and the channel B data will be strobed on the falling. I've tried to understand where that FIFO clock equation comes from, but this is the only way the math works. 

    As for the charge-pump I would just use the single charge pump setting as its internal and your divide ratio is quite small. You'll want higher loop bandwidth with the higher PFD frequency. 

    Regards

    Matt