• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 49 subscribers
  • Views 1415 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TVP5146 settings to extract 640x480 image size

Navin Reddy
Prodigy 35 points
Other Parts Discussed in Thread: TVP5146, TVP5146M2, TVP5147, TVP5147M1, DM3730

We are using TI decoder-TVP5146 to convert PAL standard (625 line) with to 20-bit 4:2:2 with separate sync signals.

The image content that we are interested in is of size 640x480. But the PAL output of the TI decoder is 864x625.

In the incoming PAL video, the image that we need to capture and process (640x480) is at the center of the 864x625 window.

Please share the register configurations to be done in the TI decoder to capture this window of 640x480 size.

 

We are planning to use the following register settings. Kindly clarify if these register settings will ensure the desired functionality as described above.

Sl No

Register Name

Default

Value that we are using

1

HSYNC Start Pixel Register

0x 0

0x 0

2

HSYNC Stop Pixel Register

0x 040

0x 040

3

VSYNC Start Line Register

0x 004

0x 004

4

VSYNC Stop Line Register

0x 007

0x 007

5

AVID Start Pixel Register

88

128

6

AVID Stop Pixel Register

808

768

7

VBLK Start Line Register

623

587

8

VBLK Stop Line Register

23

59


  • 0
    TI__Genius 16810 points

    Are you trying capture only the center portion of a standard PAL input using standard PAL sampling?

    Do you plan to use the AVID output to control capture of the active video portion?  If yes, then setting up AVID Start/Stop and VBLK will define the AVID active interval. 

    Your VBLK settings may require tweaking.  PAL is typically 576 active lines and you will need to crop to 480 active lines

     

  • 0 in reply to Larry Taylor
    Prodigy 35 points

    Yes, I want only the center portion of the PAL input.

    Yes, I am getting AVID signal as input to my FPGA.

    I am using an FPGA to capture this video. Also, I need to process the video in gray scale only.

    Hence, instead of BT.656, I am planning to use simple interface of 20-bit 4:2:2 mode with separate Sync signals. I will be capturing only Y component of the output.

    So, shall I consider that by using AVID, VS/VBLK and HS signals, I will be able to achieve my requirement?

    Also, kindly confirm if the register setting are correct?

  • 0 in reply to Navin Reddy
    Prodigy 10 points

    Hi Navin,

    This is Praveen. Working on some video application. I am new to this video applications. We are planning to go with Texas TVP5146M2 decoder IC and Lattice LFXP2 FPGA. and a camera interface. Can you please help me building an hardware for this application.

     

    My mobile number: 9866339896

    mail:praveen@sumith.in

  • 0
    Prodigy 60 points

    Hi Navin,

    I am using the similar chip TVP5147 and I just want to know how do you set up the chip to output both VBLK and VS signals at the same time. The pin only allows you to output only either VS or VBLK signal.

    Thanks,

    Nguyen Ha

    Trident Systems Inc.

  • 0 in reply to Larry Taylor
    Prodigy 60 points

    Hi Larry,

    I am using a similar chip, the TVP5147M1 video decoder with a standard 720x480 NTSC input signal. My question is how do you get both VBLK and VSYNC to output at the same time since the pin on the chip only let you select either function VS or VBLK not both.

    I am having to generate the VS signal manually based on VBLK and it's not working because I am always a little off as far as the exact location of the VS pulse in the frame.

    Thanks,

    Nguyen Ha

  • 0 in reply to Larry Taylor
    Intellectual 320 points

    Hi

       Larry

     

       I want to use tvp5146m2 input 723x579 sizer , crurent dm3730 tvp5146m2 bt565 (with embedded sync mode)input sizer 720x579,720x576 is ok.

      The omap-resizer to resizer 720x576 input must be 723x579. So  i need input 723x579.

     Change the tvp514x-int.h

       /* Number of pixels and number of lines per frame for different standards */
       #define NTSC_NUM_ACTIVE_PIXELS        (723)
       #define NTSC_NUM_ACTIVE_LINES        (483)
       #define PAL_NUM_ACTIVE_PIXELS        (723)
       #define PAL_NUM_ACTIVE_LINES        (579)

        kernel errors:

       omap3isp omap3isp: isp_wait: wait is too much
    omap3isp omap3isp: ccdc 1 won't become idle!
    omap3isp omap3isp: omap34xx_isp_isr: sbl overflow, sbl_pcr = 00800000
    omap-iommu omap-iommu.0: omap2_iommu_fault_isr: da:0019b340 translation fault
    omap-iommu omap-iommu.0: iommu_fault_handler: da:0019b340 pgd:cf930004 *pgd:8fba9801 pte:cfba9a6c *pte:00000000
    omap3isp omap3isp: omap34xx_isp_isr: sbl overflow, sbl_pcr = 00800000
    omap-iommu omap-iommu.0: omap2_iommu_fault_isr: da:0019b340 translation fault
    omap-iommu omap-iommu.0: iommu_fault_handler: da:0019b340 pgd:cf930004 *pgd:8fba9801 pte:cfba9a6c *pte:00000000
    omap3isp omap3isp: omap34xx_isp_isr: sbl overflow, sbl_pcr = 00800000
    omap-iommu omap-iommu.0: omap2_iommu_fault_isr: da:0019b340 translation fault
    omap-iommu omap-iommu.0: iommu_fault_handler: da:0019b340 pgd:cf930004 *pgd:8fba9801 pte:cfba9a6c *pte:00000000
    omap3isp omap3isp: isp_wait: wait is too much