Original question:
It is not clear in the datasheet but could you please confirm:
| Data Rate | Min f_clk |
| 4 MSPS | 32 Mhz |
| 2 MSPS | 16 Mhz |
| 1 MSPS | 8 Mhz |
I have configured the ADS1675 for CMOS and therefore I am limited to 1 MSPS.
I understand that that the min/max specs for the ADS1675 is for 32 Mhz, but are there any major disadvantages to using an 8 Mhz clock vs a 32 Mhz clock?
Hello McCain,
Welcome to the TI E2E community!
The data rates specified in the datasheet are based on an input clock of 32MHz, and will linearly scale for each DRATE setting. The lower data rates average additional input samples as the data rate is reduced, which results in lower noise and higher dynamic range, per Table 1 in the datasheet.
If setting DRATE to 0x011b, then in order to get 1MSPS, f-CLK must be set to 32MHz. If f-CLK=8MHz, then the actual data rate will be reduced by a factor of 4, or 250ksps. You will get a slightly lower power consumption using a lower clock speed, but we do not specify this condition nor have data for this condition.
You could use f-CLK=8MHz and set the DRATE to 0x000b to maintain 1MSPS, but then the data converter would automatically switch to high-speed LVDS mode, and you would no longer be able to use the CMOS interface.
Regards,
Keith Nicholas
Precision ADC Applications
