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TPL0401A-10-Q1: I2C Communication Timings

Part Number: TPL0401A-10-Q1
Other Parts Discussed in Thread: TCA9537

Hello,

are the timing requirements in the table chapter 7.6 requiremens to the master µC that the TPL0401 will undestand the messages or is it just the timing, that the TPL0401 will generate when we read back the wiper position? I expect it is for both, because it also contains SCL values that will not be generated by TPL0401, right?

Will the TPL0401  automaticaly select between standard mode and fast mode? E.g if I use 95 kHz it could from frequency point of view work with both modes. If I measure for the µC I2C for tSPS 3,7 µs it would be ok for fast mode (>0,6 µs) but not for standard mode (>4 µs).

second more critical is with tVD (DATA) I have a bigger problem for both modes, in the datasheet  is writen tVD (DATA) must be for both modes <1 µ, on the picture I expect it is marked as tvd (wihout Data but it is below the Data Bit 7) on Figure 9, right? But on the µC I measure at the moment depending on falling or rising edge 1,7 - 2 µs what would be longer than max value. On the answer Data we see that the tvd from TPL0401 is below the 1 µs.

Do you see here any issue? Isn't it more important, that the SDA Signal is valid High/Low befor SCL starts rising and not important that is is valid bevore 1 µs after the SCL is falling?
On our borads we did not see any communication problems until know, but we also did not check all edge cases  like Temperature and so on.

Thank you for a fast answer.

  • Hello again,

    ini some other datasheets I also see that for standard mode tVD max is given as 3.45 µs and for fast mode as 0.9 µs (TI TCA9537 and also I2C from other manufacturers).
    can it be that 1µs for standard mode is a bit tide in this device? Can you please double check if this is true?

    Thank you very much.

  • Hi Jens, 

    We are double checking this and should be able to provide a response after the weekend. 

    Best,

    Katlynne

  • Hi Jens, 

    Your use case should be fine. 

    Both. I2C requires the coordination between both the controller and the peripheral device. In that case the timing should be communication back and forth.

    Devices that are fast mode capable are downward compatible. Because this device is usable for fast mode systems, it should be accessible for standard mode as well. Generally, fast mode systems, have a few changes compared to standard mode. There are spike suppression and a Schmitt triggers for the pins and also slope control for the falling edges of these pins. The SDA and SCL pins must be floating when the power is removed and pull-up devices scaled accordingly for the faster rise times.

    The tvd is the data valid time. I think you would want to read this as a maximum, where 1us is the longest amount of time that it would take to make sure the data is valid from.

    Best,

    Katlynne Jones

  • Hello Katlynne ,

    thank you for your answer.

    You mean in the datasheet it is correct that for STANDARD MODE and for FAST MODE max 1µs fir tVD is correct? In the NXP I2C definition for standard mode it is allowed to have more time.

    On our µC I measure 1.7 µs to 2µs what is longer than the Texas instruments allowed maximum of 1 µs but less than in the I2C Standard 3.45µs.
    According to your answer this would still be fine even if it is outside of Texas Instruments datasheet spec?
    yellow is SCL,
    green is SDA

  • Hi Jens, 

    In the I2C standard, the maximum data valid time is 3.45us so that the setup time + rise time can occur in the minimum SCL low time of 4.7us. If a peripheral took longer than 3.45us for data to be valid, then the setup time would not be met for the 4.7us low time of SCL. The DAC will take no longer than 1us for data to be valid in both standard and fast mode. As long as the controller is meeting the setup time required by the DAC + transition time within the SCL low time then there should not be an issue. 

    Best,

    Katlynne Jones