What is the meaning of minimum bandwidth of the driving amplifier for ADS8556, datasheet told me 6.7MHz from equation1. If I design active low-pass filter to cutoff frequency at 100Hz before ADS8556 CH_X, am I still got 280ns (minimum acquisition time) from ADS8556.
Thank you.
Hello Panut,
The required bandwidth of the amplifier can be calculated using the equation provided on the datasheet as a function of the acquisition time. The acquisition time may vary with the data rate used.
The formula given in the datasheet gives an approximation of the required amplifier's frequency response in order to charge the input capacitance of the ADS8556 within the acquisition time. The input capacitance is 10pF for the +/-4VREF mode or 20pF in +/-2VREF mode. The acquisition time varies as a function of the data rate used. At maximum data rate, the required minimum acquisition time is 280ns; which in this case requires a minimum required bandwidth for the driving operational amplifier of 6.7MHz for the ADS8556 (16 bit).
The data rate is a function of the conversion time + acquisition time. The device can use either the internally generated or an external (XCLK) conversion clock signal. The external conversion clock can be up to 20MHz. In both cases 18.5 conversion clk signal cycles are required for a conversion. The maximum conversion time is 1.26us (microseconds). The minimum aquisition time is shown in the parallel read acces timing diagram below where at maximum data rate is used giving the minimum acquisition period of 280ns. In your application, if you are using a longer acquisition time (using slower data rate), the minimum required bandwitdth of the driving amplifier can be calculated.
Please see parallel read access plot below.
Regards,
Luis
