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ADS1220: When the IC is powered down, is the SPI bus input pins high impedance?

Part Number: ADS1220

Hello  : )

I was wondering if you can help me. I currently plan on having several SPI devices on the same bus - and some of these devices including the ADS1220 can have their supplies powered down. I'd like the devices on the bus that are powered to remain accessible

Would you know if the SPI input pins (clock and Din pin) are high impedance when the IC is fully powered down?

In the data sheet I can only see that the input leakage on these pins is +-10uA for a logic low/high but as far as I can tell this assumes the IC is powered up.

For the Dout pin, my plan currently is to put a SN74LVC1G125DBVR non-inverting buffer with 3-state output. The CS line would drive both the ADS1220 as well at the 3-state control on the buffer. I'd do this for all the devices on the bus.

Cheers!

Adam

  • Hi Adam,

    The overall problem with this scenario is the Absolute Maximum Ratings requirements.  The input pins have ESD structures that will drive current through the device from the digital signals.  As the ADS1220 is relatively low power, back driving current back through the device can place the device in an odd operating state and may actually attempt to power up the device as current moves through the ESD diodes back to the supply pins where caps will start to charge.

    So in general you don't want any signal either analog or digital to be driving the input pins while the ADS1220 is unpowered.  The design alternative is to use the POWERDOWN command.

    Best regards,

    Bob B

  • Sorry for the late reply! Thank you for looking into this : )