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ADS1263: SPI bus setup and hold timing

Alexander Eaton
Prodigy 10 points
Part Number: ADS1263


I need to verify the setup and hold times for SPI bus between TMS320 and ADS1263. I believe I found an issue with my design, where the SOMI setup time is not guaranteed by the ADS1263 datasheet. Could you please confirm whether I am understanding the datasheets correctly?

TMS320 Configuration:

SPI Port = A, SPIA CLK = 7.2MHz, High Speed Mode = Disabled, CPOL=0, CPHA=0 (Rising Edge Without Delay)

Based on CPOL and CPHA, data is updated on rising clock edge, and sampled on falling clock edge.

TMS320 SOMI Setup Time Requirement = 20nS (ref datasheet pg 163)

ADS1263 SOMI Setup Time Characteristic = (SPIA CLK Period / 2) - Tp(SCDO) = (138.89nS / 2) - 60nS = 9.44nS

SOMI Setup Time Margin = 9.44nS - 20nS = -10.56nS

ADS1263 Timing Diagram:

  • 0
    TI__Guru 54166 points

    Hi Alexander Eaton,

    I am a bit confused by your question, so please correct me if I missed something

    Why are you concerned about the MISO requirements for both the controller and the ADC? Shouldn't you be considering the MOSI requirements for the controller when you are concerned about the MISO requirements of the ADC (and vice versa)? The MOSI setup time for your controller looks to be on the order of 1-2ns, depending on your conditions, which is more than enough time given the ADC MISO setup time and your SCLK speed

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 10 points

    Hi Bryan,

    I am concerned specifically about the setup time for the slave (ADS1263) sending data to the master (TMS320), i.e. the SOMI setup time. My understanding of the datasheets for the two parts is that the TMS320 required SOMI setup time is minimum 20nS. The ADS1263 SOMI setup time Switching Characteristic is 9.44nS (as described above). So the device receiving data requires data to be valid 20nS prior to latching data in, but the device sending data only guarantees that data will be valid 9.44nS prior to data being latched by the receiving device. I would like to know if my analysis is correct?

    Thanks,

    Alex

  • 0 in reply to Alexander Eaton
    TI__Guru 54166 points

    Hi Alexander Eaton,

    Thanks for clarifying - which processor are using specifically? I searched through a few TMS320 datasheets, none of which had switching characteristics on page 163 (and none that were at 20ns setup time)

    I believe you are interpreting the specs correctly. Are you able to slow down the SCLK speed to meet the requirements? Slowing down to 6 MHz seems like it would meet the requirements

    -Bryan