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ADS1220: ADs1220 clock deviation

Eric Liu(SZ-FAE)
Intellectual 1595 points
Part Number: ADS1220


Hi team,

In my customer application, the use the ads1220 with internal clock and the sps is been set as 1000 sps but for many ads1220 devices. Some will be 980 sps and the others may be 1020 sps , the clock pin connected to gnd by 0 Ω resistor, what will cause this , i think the 0 Ω resistor may affect this.

  • 0
    TI__Guru** 113765 points

    Hi Eric,

    Can you put the customer name and any project information in the Notes section at the top of the thread?

    The listed data output rates are not exact and are often rounded off to a near value.  The actual conversion times are listed in Table 11 of the datasheet.  In normal mode and continuous conversions for 1000sps, the actual conversion time is 4144 tclk periods (tclk = 1/fclk = 1/4.096Mhz).  The actual nominal output rate is 988.4sps and is typically +/-1% but can be as much as +/-2%.

    So it would be considered normal for the output rate to be between 968.6sps and 1008.2sps.  Seeing a value of 980sps is normal and within typical response.  1020sps would be considered a bit high.  How is the conversion period being measured?  It should be from the falling edge of DRDY to the next falling edge of DRDY.  When using an oscilloscope to measure I would recommend using the setting that would capture the time between 2 DRDY falling edges and setting the scope to a single triggered event as opposed to auto-trigger mode.

    Using a 0 Ohm resistor on the CLK pin is fine or you can connected directly to ground if not being used.  One other consideration is making sure you follow the DVDD ramp timing shown in section 10.2.  If the timing  is not met the device may not be in the correct operating state, and a RESET command should be issued to restart the device.  I would recommend using the RESET command to see if oscillator timing changes.

    Best regards,

    Bob B