Hello,
One customer used our high speed ADC with signal sampling board application, but the sampling reference clock is not stable. The frequency of the sample reference clock fluctuates between approximately 100MHz and 300MHz, and the fluctuation is a periodic,it changes one cycle from 100M to 300M at approximately every 10us . Does the chip currently support the input of a continuously changing working clock, if so, what is the state of the output data and the clock ?
Best regards
kailyn