DAC121C081: Randomly no ACK on Write or Read

ADR0 is floating

VA source is LM4132AMF-4.1/NOPB

we are reviewing now.

Hi Howard,

What are you using for your I2C voltage? What potential is the DAC using for the supply vs the I/O voltages? Have you confirmed with an oscilloscope that the bus is reaching the VIL/VIH thresholds?

What I2C address are you using?

Thanks,

Paul

I am using 3.3V for the I2C voltage. The DAC was using 4.1V VA. I realized that the VA voltage was too high for the 3.3V I2C voltage to reach the thresholds. I have changed the DAC VA voltage to 3.3V but, I am still having issues. 

Address 00011000

I am trying to update an image of the circuit, but it keeps telling me it is not allowed to be inserted.

So I think you are using one of the floating address:

We have seen some systems have issues with the floating addresses due to excess flux on the PCB forming a leakage path that might pull the pin low or high.  For an experiment, can you ground the address pins and check if communication becomes more reliable?

I will try this right away. Does the DAC require the change I made from 4.1V to 3.3V on the VA pin for proper functionality?

I grounded ADR0 (pin 6) by connecting it to GND (Pin 3) and incremented the address by one. It still randomly fails.

I noticed this note in the spec sheet for the SDA in:

Serial Data bi-directional connection. Data is
clocked into or out of the internal 16-bit register
relative to the clock edges of SCL. This is an
open-drain data line that must be pulled to the
supply (VA) by an external pullup resistor.

The SDA Line is pulled up to the I2C 3.3V source. This is not the same as the 3.3V Reference used to power the VA pin. Does it need to be pulled up to the VA pin as well?

This seems to be some kind of initialization issue. If it powers up working, it continues to work. If in powers up not working, it does not start working.

As long as two voltage are very similar, it should be fine to have different pull-up potentials.  

Have you been able to capture the failed ACK with an oscilloscope?

Yes, but I can't seem to be able to post them .

Can I email them to you?

yes, frost@ti.com. 

Does your supply ramp up monotonically?

Email sent

I sent another email with the power up waveforms and the schematic snippets.

Hi Alan, 

Paul is out of office for the holidays and will review the schematics and waveforms next week when he returns. 

Best,

Katlynne Jones

Thank you Katlynne, Is he back on 1/2 or 1/8?

Hi Alan, 

He is back on 1/8. 

Can you email me the files at 

Best,

Katlynne Jones

I tried a couple more things people suggested.

Clock 18 high values to the I2C bus to clear/reset parts. This did not appear to work but not sure I had the timing right.

Try the other addresses. So, I changed my code to try the wired Address and if it fails, try the other addresses. On this one unit this appears to be making it work. So, this seems like some kind of a DAC power up address setting problem.

Hi Alan, 

Thanks for the additional information. I think it would be good if we could review your power up sequences and the timing. You can share those to my email. 

Best,

Katlynne Jones 

Waveforms sent.

Hi Alan, 

There seems to be a very large negative glitch on VA to almost -4V. This could be damaging the parts. This also could explain why replacing the part does not always fix the issue, as you could be damaging the new parts as well. 

Is there a way to avoid this glitch on startup?

Best,

Katlynne Jones

I sent an email with schematics regarding the startup glitch.

Hi Alan, 

Thanks for the schematic. Is there any way you can disconnect VA from LM4132AMF-4.1/NOPB and connect a power supply to the DAC  directly? This way we can check if the issue is a result of the power on glitch or something else. 

Best,

Katlynne Jones

Hi Katlynne,

Do you mean an external standalone supply?

Alan

Hi Alan, 

Yes, sorry for not clarifying. We'll know the issue is from something else if the issue still occurs when the DAC is supplied with an external supply with a clean ramp up.

Best,

Katlynne Jones

I have tried the external power supply. The unit worked normally running on the external supply. I reconnected the VA in the circuit and the unit still worked normally. I have not been able to make the unit fail with the internal or the external supply now. I will keep testing.

We are still having issues. Any suggestions for updating the circuits to prevent the power on glitch?

I would assume the supply ramp is non-monotonic due to inductive loading on the supply source and output impedance on the supply path.  If it follow your schematic correctly, you have some series resistance on the VA supply, and some inductors on the path to ground - is that correct? can those components be removed? The alternative could be add capacitors on the VA input of the DAC that are very large, these will increase the inrush current, but make any inrush current of the device less consequential.  Can you try to add >100uF on the DAC VDD pin for a test?

Hi Paul,

Thanks for the suggestion.

VA is generated by U52 (DC_VDD)

VA Series Resistance: Not sure what resistor you are referencing?

Inductors on path to ground: Are you referring to L5 and/or R220?

We are testing a modification that disconnects the U52.3 (Reference Voltage IC) enable pin from the +5V source. Then connect it to a 100K Resistor to the +5V source and a 1uF capacitor to ground so the enable pin has a power on reset function. So far it seems to help. Do you see any issues with this modification?

Hi Alan,

That seems prudent.  The only issue with using an RC filter as a reset/enable pin is that the ramp time is very long, and it is possible that the input voltage is between the VIH/VIL input region, which can cause the pin to sink extra current.  I dont foresee this as a major concern, but you might consider adjusting the RC until the delay is a minimal as possible.

We are changing the U52 reference to a 3.3V part instead of a 4.1V part. Over a second after the initial "problem" glitch the VA ramps high over 40mS which should start the RC time constant (100mS). The U52.3 reference pin should go high after U52 is powered. Is the VIH/VIL input region the time between the enable being seen as a low and time seen as a high?