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AFE5401-Q1: Is SDOUT terminal high-impedance when SEN is L level? Or is SDOUT kept active(no high-impedance)?

Kazuya Nakai59
Guru 21765 points
Part Number: AFE5401-Q1


Hello guys,

One of my customers is evaluating AFE5401-Q1 for their next products.

At this moment, they have the following question.
Could you please give me your reply?

Q.
Is SDOUT terminal high-impedance when SEN is L level? Or is SDOUT kept active(no high-impedance)? 

Your reply would be much appreciated.

Best regards,
Kazuya.

  • 0
    TI__Expert 4711 points

    Hi,

    By default SDOUT buffer will be in Hi Z state. Whenever device goes in read mode on programming REGISTER read mode enable bit to "1", SDOUT will become active. What is the observation customer having?

    Thanks!

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Guru 21765 points

    Hi Shabbir,

    Thank you very much for the prompt reply.

    They connect other SPI device output to AFE5401-Q1 SDOUT for common using of the data line.
    They thought SDOUT terminal became high-impedance when SEN is L level. 
    They found that SDOUT is not in high-impedance mode because SDOUT voltage was 1.8V though their expect was 3.3V. 
    (I think it was signal     collision.)

    But they thought is wrong according to your reply.
    I will tell them to set "0" to Register 0(00h) bit1 (REG_READ_EN bit) when they want to change SDOUT from active to high-impedance state.

    Thank you again and best regards,
    Kazuya.  

  • 0 in reply to Kazuya Nakai59
    Guru 21765 points

    Hi Shabbir,

    Thank you very much for your supports,

    The customer controls Register 0(00h) bit1 (REG_READ_EN bit) like the follows.
    But the SDOUT state can not be changed to high-impedance.

    Could you please tell me which point is wrong?

    [The customer test procedure]

    1. Removed SDOUT output line from other device output.
    2. Added 10kohm between SDOUT and GND (=pull down resistor).
    3. Write data, 0x0000 to a    ddress 0x00 (write mode is set)
    4. Write data, 0x8101 to address 0x1D (data writing).
    5. Write data, 0x0002 to address 0x00 (read mode is set)
    6.     Read data from address 0x1D (read mode is set)
    7. Read data from address 0x1D -> 0x8101 was read.
        At this moment, SDOUT=H state.
    8. Write data, 0x0000 to address 0x00 (write mode is set)
        At this moment, still SDOUT=H state.

    The customer think if SDOUT becomes high-impedance, SDOUT level must become to "L" by the pull down resistor.

    Could you please check if the procedure is correct and could you please give me your comment?

    Now the customer think SDOUT doesn't have high-impedance mode. Is the customer thought correct?

    Thank you again and best regards,
    Kazuya. 

  • 0 in reply to Kazuya Nakai59
    TI__Expert 4711 points

    Hi,

    I could follow customer observation. It does seem that SDOUT is not going to HiZ state. I will cross check in design. I will get back in first week of Jan as next week many engineers are on leave.

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Guru 21765 points

    Hi Shabbir,

    Thank you very much for your reply.

    I see. I 'm looking forward to receiving your next reply.

    Thank you again and best regards,
    Kazuya.

  • 0 in reply to Kazuya Nakai59
    TI__Expert 4711 points

    Hi,

    Wish you a very happy new year.

    We checked in the design and found that SDOUT buffer is always enabled and it is not going to high impedance state. So your observation is correct. In this device SDOUT buffer is always active and SDOUT pulled to ground by default.

    Thanks!

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Guru 21765 points

    Hi Shabbir,

    A happy new year. 
    And I'm sorry to be late my response because I took long new year day off.

    Thank you for your strong supports.
    I understood it.

    Thank you very much again and best regards,
    Kazuya.