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TSW1400 internal PLL demands high quality FCLK or DCLK?

Xiaochen Xu
Prodigy 75 points
Other Parts Discussed in Thread: AFE58JD28

Team, 

we are running the TSW1400. We found that FCLK is presented at Samtec connector, but its waveform is not nice. from time to time, USER_LED3  is ON and off (indicates the FPGA PLL1 is locked to the ADC input clock from port 0)

This makes me thing that TSW1400 requires good clock.  our FCLK is 40MSPS, DCLK is 240MSPS.I think TSW1400 is using FCLK to get internal PLL run. just want to double confirm. 

The measured FCLK is shown below. 40MHz is from our system board and 50Mhz is from TI EVM. certainly TI AFE/ADC EVM signal is better. ours have long traces and several connectors in between. Any idea? 

I will work on clock circuit to slow it down and see . 

Thanks a lot!

Xiaochen

  • 0
    TI__Mastermind 23920 points

    Hi Xiaochen,

    The FPGA on the TSW1400EVM uses the DCLK as PLL input typically, however the firmware being used may use the FCLK instead. Which device is used? You mentioned ADC and AFE, could you be more specific? Something to try is to slow the sample rate down (to reduce DCLK) to within 200MHz bandwidth of the oscilloscope and probe those signals? My guess is that the DCLK signal integrity is the more important signal related to PLL locking, not the FCLK, but knowing which device would allow us to check. Signal integrity may be better at low speed and you may find that the PLL locks more frequently. 

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 75 points

    Thanks chase! We are using AFE58JD28. This explains my doubt. I have both TSW1400 and TSW1405. I know 1405 uses the FCLK to generate PLL clocks. So 1405 can capture some data, just not quite right data. I will slow the ADC CLK down and see. 

    Thanks a lot!

    Happy Holiday!