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AFE58JD48: JESD204B Multiple ADC Synchronization

alen
Prodigy 80 points
Part Number: AFE58JD48
Other Parts Discussed in Thread: LMK00301, LMK04832

hello:

   I am planning to synchronize multiple AFEs with JESD204B. Currently, I encountered some issues in PCB design as shown in the picture. I am using LMK04832 to output DEVICE CLK and SYSREF signals, and then fan them out to AFEs and FPGA through LMK00301. I known that each group of DEVICE CLK and SYSREF signals should be  length match such as dclk0 and sysref0. Question is, should DCLK0, DCLK1, DCLK2 also be length match or unnecessary? And for the sync_n signals output from FPGA, such as sync_n0 and sync_n1, do they need to be  length match?

thanks

  • 0
    TI__Expert 4711 points

    Hi,

    Wish you a very happy new year.

    You must be using subclass 1. In that case deterministic latency is not guaranteed by SYNC signals so you dont need to do length matching for SYNC signals.

    DCLK0/1/2 doesnt need to be length match until you want same sampling time instant across devices. 

    Thanks!

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 80 points

    Thank you, the same to you!

    It is difficult to make length matching for DCLK0, 1, 2... The current wiring may cause a timing difference of 1ns between different chips, but it should not be a big problem.