the output DAC5682Z

Hi Steven,

First of all, I'm a little confused about your application. As I read it, it looks like you want to achieve 64-bit performance by using four 16-bit DACs and combining the outputs. Is this correct? If so, you aren't going to be able to get the performance you expect. If this is not correct, can you send me your reference design? Also, what is the frequency of the signal you're trying to output?

As far as your questions go:

1. If you give the DAC 16-bits, the output is going to be 16-bits and the SNR performance will be based on 16-bits.

2. Can you send me plots of your waveform? I'm not sure what you mean by "if the input others".

3. When used in dual DAC mode, the data is clocked in for DAC A on the DCLK rising edge and data for DAC B is clocked in on the DCLK falling edge. This is shown in figure 33 on page 35 of the datasheet.

Regards,
Matt Guibord

Hi, Matt Guibord,

Thanks for your reply. Actually, the board is designed by others, and no document is left. The DAC board consists of two DAC 5682Z, and the outputs have four channels.  I just use the DAC board to output my calculation results, which is 32-bit for each data. Now what I have is the interface program for FPGA and a sine ROM data, which is attached. In the program DAC_IF.v, the signal " DAC_BUF_DATA" is the input data for DAC board, and other signals: DAC_RESETB , DAC_SDENB, DAC_SCLK, DAC_SDIO, DAC_SDO is generated by another module.  The problem is :

(1) When the system reads a sine wave data from a ROM, and input into DAC board, the DAC board can output stable sine wave in four channels. I can watch them by an external oscilloscope. How to get the sine data in the ROM?

(2) When the system reads our calculation results from a RAM, there are no stable waveform output from the DAC board. If our calculation results is 32-bit, how to arrange the data format  according to the current design, and output the calculation results in four channels? For example, we can choose the first 16 most significant bits as the DAC input, but how to arrange them for two DAC chips?

Best Regards.

steven

Hi Steven,

Thank you for the additional information. I'm still confused about what you're trying to output. You say that you have a calculated result that is 32-bits and you want to output 16 bits to each DAC. What is this calculated result? Is it a single 32-bit number that you're trying to output as 32 bits using two 16-bit DACs (by combining their output or something)? Can you clarify this? This is the statement that confuses me: "For example, we can choose the first 16 most significant bits as the DAC input, but how to arrange them for two DAC chips?"

Second, what is your expected output signal? You say that your calculated results do not result in a stable waveform, is it possible that your calculated results do not form a stable waveform?

Lastly, what are the numbers in the .coe file? Are these the ROM values?

Regards,
Matt Guibord

Hi, Matt Guibord,

Thanks for your reply. I am sorry I do not clarify my case. Actually, FPGA will generate some data, and each data is 32-bit. The 16 most significant bits of each data are output by DAC board, which consists of two DAC5682Z chips. What is the data format between DAC_IF and DAC? In an other word, for one DAC5682Z, it  transfers data for two channels by DDR mode, and then the input data are 64bits ( 16 bit x4).  What is the format of this 64-bit data? Is it according to the data diagram mentioned in Page 35 in data sheet?

(2)The numbers in the .coe file are the ROM values, which is a sine wave. Now when system reads the ROM values and output through DAC board, a sine wave can be watched by an external oscilloscope. But the DAC board is used to output our calculation data, the output waveform is not stable. Actually, the calculated results can form a stable waveform.

Best Regards.

steven

Hi Steven,

I think I understand now, but let me clarify. You are calculating four 32-bit values and the 16 most significant bits of each value is going to go to one of the DACs. Is this correct? It sounds like you have one board that calculates the results (DAC_IF) which then sends the four results (16 bits per DAC times 4 DACs = 64 bits total) to your DAC board that has two DAC5682z's on it.

The one thing that is confusing me is that the DAC5682z uses a dual data rate clocking scheme as shown in Figure 33 on page 35. Channel A clocks in on the rising edge of DCLK and channel B clocks in on the falling edge. Both channel A and B use the same data pairs so for four DACs (two DAC5682z's) you would only need 32 data pairs (or 64 data lines total) where 16 pairs go to one DAC5682z and the other 16 go to the other. You keep mentioning 64-bits so I'm not sure if you're referring to the number of data lines (two lines per data pair) or data pairs. It would be very helpful for you to draw out a block diagram of your system including the number of physical traces between the two boards.

As far as the format for the data, this DAC can use either offset binary or two's compliment depending on their register settings. The data you're sending to the DAC needs to be in the correct format. For instance, if offset binary is used then the data needs to be encoded as values 0x0000 to 0xFFFF (with 0x8000 being zero, all numbers below are negative, all numbers above are positive). 0x0000 is the most negative number and 0xFFFF is the most positive number.

Lastly, is the ROM on the DAC board or the DAC_IF board?

Regards,
Matt

Hi, Mat Guibord,

Thanks for your reply.  You are correct. The calculation results are 32-bit, and the 16 most significant bits are chosen to output through a D/A board, which consists of two DAC5682Z.  The program DAC_IF is the interface module to D/A chip. In the DAC_IF, the signal "DAC_BUF_DATA" is the data to be output by D/A, which is generated by another module in FPGA.   From the program DAC_IF,  the signal "DAC_BUF_DATA" is generated by 100MHz, but DCLK is 200MHz, and data is transfered by DDR mode, then a 64-bit data (64 pairs) is for a DAC5682Z chip. But how to arrange this 64-bit data? According to the page 35 in data sheet, I think in the signal "DAC_BUF_DATA", the bits 0-15 and 32-47 of are for channel A, and the others are for channel B. How do you think?

(2) The ROM moule is in FPGA, and a sine wave is stored it. when you open the .coe file, you find that each data is 64-bit, and the 512 sample consists of an one-period sine wave. But I do not know how to calculate the data values in  the .coe file.  If we know how to get these values, the data format and how to arrange four 16-bit input data can be derived. I am sorry I also have no enough document about it. Actually, the data in the ROM can be output by D/A, and it works well. A sine wave can be watched by an oscilloscope.

Best Regards.

steven

Hi, Matt Guibord,

Thanks for your reply and suggestion. I have solved the problem of data format and how data are transfered into DAC chip. Do you remember the .coe file I uploaded before? which is a sine wave stored into a block ROM inside FPGA. Now when the sine wave is read from ROM and output by DAC, the waveform is stable on displaying by a oscilloscope. But when I put my own data in the block ROM, such as the calculation results, the waveform on the oscilloscope is not stable. It seems that the waveform is disturbed by noise. Do you give me some suggestion how to solve this problem?

Steven,

Can you provide a screen shot of what you're seeing? As well as either a description or a plot of what you're trying to output (single frequency sine wave? multi tone?).

Regards,
Matt Guibord

Dear Matt Guibord,

Thanks for your kind help. The attachment is the a video on waveform on oscilloscope when the data in the block ROM is changed to our calculation results. I am sorry the video is taken by my mobile phone. You need  the software "Quick Time" or "iTunes" to play it. Actually, the waveform is cyclic, and only one period is stored in the block ROM.  Due to limitation of uploaded file size, I will upload another video when the data in the block ROM is one period of a sine wave.

best regards

steven

Dear Matt Guibord,

The attachment is the a video when a sine wave data are stored in the block ROM.

Best Regards.

steven

Steven,

Did you store the same number of samples and a full period into the EEPROM as the original was?

It sounds like the data is being pulled out of the ROM automatically. If there was originally a full sine wave period stored in it, the frequency of the sine wave will depend on the clock speed. If you replace that full period with your own signal that is not a full period or not the same number of samples, I would expect the output to be distorted.

At this point, you should be outputting directly from your FPGA to the DAC and not going through the ROM (assuming your architecture allows this). Its not as simple as just writing to the ROM since it must be a full period, a coherent signal, the correct number of samples (or a way to change the number of samples before resetting the ROM index) and such.

Regards,
Matt Guibord

Hi, Matt Guibord,

Thanks for your reply.  In the ROM, the data are one period, even if our calculation data. Firstly, I output our data from FPGA to DAC directly, the waveform on oscilloscope is not stable, and same as the waveform on the video. And I also change the samples in the ROM or decrease the clock frequency of the output data, the waveform is still not stable. I have no idea about this. Please give me some suggestions.

Best Regards.

steven