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DAC37J82: 8b/10b disparity error & no data out from DAC

Ashley G
Prodigy 10 points
Part Number: DAC37J82

Hello, I'm having some issue initializing the DAC37J82 device.

What I'm trying to do is set up two JESD lanes on the SERDES lane0 & lane1 (RX0 and RX1) inputs, assign them to JESD lanes 0 and 1 in a single link0, pass them through the A & B data paths, and send them out the IOUTA and IOUTD pins. The input to the DACCLK pins is running at 250 MHz, and the JESD is intended to run at 2.5 Gbps, LMF=222.

I seem to be getting odd disparity issues after configuration and no data coming out of the DAC. Strangely enough, when I try the /K28.5/ test, it seems to pass in the device.

Standard operation: SYNC occasionally goes low in a repeated pattern, but stays high most of the time. 0x64 and 0x64 status registers read back 0x100 (8b/10b disparity error)
/K.28.5/ test mode: Stable SYNC (always high), 0x64 and 0x64 read back 0x0000 (no errors).
/D.21.5/ test mode: No SYNC, 0x64 and 0x65 status registers read back 0x400 (code synchronization error)
Repeating ILA test mode: SYNC occasionally goes low in a repeated pattern, but stays high most of the time, similar to standard operation. 0x64 and 0x64 read back 0x0000 (no errors).

If it helps, here's the initialization sequence I'm sending to the DAC:

1. Reset DAC pin via pin
2. Program DAC registers with these values:

Reg | Value
{ 0x23, 0x01ff }
{ 0x1A, 0x0026 }
{ 0x31, 0x1800 }
{ 0x32, 0x0000 }
{ 0x33, 0x0000 }
{ 0x3D, 0x0088 }
{ 0x3E, 0x0148 }
{ 0x3B, 0x0000 }
{ 0x3F, 0x0000 }
{ 0x46, 0x0044 }
{ 0x47, 0x190a }
{ 0x48, 0x31c3 }
{ 0x49, 0xFFF0 }
{ 0x4A, 0x0320 }
{ 0x5F, 0x0123 }
{ 0x60, 0x4567 }
{ 0x24, 0x0000 }
{ 0x25, 0x2000 }
{ 0x00, 0x211A }
{ 0x03, 0xf300 }
{ 0x4A, 0x033e }
{ 0x4B, 0x1f01 }
{ 0x4C, 0x1f01 }
{ 0x4D, 0x0100 }
{ 0x4E, 0x0f0f }
{ 0x4F, 0x1C61 }
{ 0x50, 0x0000 }
{ 0x51, 0x00DC }
{ 0x52, 0x00FF }
{ 0x53, 0x0000 }
{ 0x54, 0x00FC }
{ 0x55, 0x00FF }
{ 0x5C, 0x0008 }
{ 0x5C, 0x0000 }
{ 0x61, 0x0211 }
{ 0x22, 0x101C }
{ 0x02, 0x2002 }
{ 0x04, 0xFCFC }
{ 0x05, 0xEFF7 }
{ 0x06, 0xFFFC }
{ 0x14, 0x0000 }
{ 0x15, 0x0000 }
{ 0x16, 0x8000 }
{ 0x0C, 0x01B0 }
{ 0x0D, 0x0000 }
{ 0x0E, 0x0000 }
{ 0x0f, 0x0000 }
{ 0x1E, 0x9999 }
{ 0x1F, 0x8882 }
{ 0x1F, 0x8880 }
{ 0x20, 0x8008 }
{ 0x26, 0x0000 }
{ 0x2D, 0x0001 }
{ 0x3C, 0x0050 }
{ 0x64, 0x0000 }
{ 0x65, 0x0000 }
{ 0x66, 0x0000 }
{ 0x67, 0x0000 }
{ 0x68, 0x0000 }
{ 0x69, 0x0000 }
{ 0x6A, 0x0000 }
{ 0x6B, 0x0000 }
{ 0x6C, 0x0000 }
{ 0x4A, 0x0321 }

3. Enable DAC TX via pin
4. Enable JESD TX from master device

  • 0
    TI__Mastermind 23760 points

    Hi Ashley,

    The first thing I notice is you are wanting a 2.5Gbps line rate, but this is not achieved with 2 lanes, You would need to use 4 lanes to accomplish 2.5Gbps serdes. The line rate calculation for this device is:

    Serialized Data Rate = Fdata * 16 * (10 / 8)

    If Fdata = 250MSPS (input data rate to the DAC), the serdes rate is 250*16*10/8=5000Mbps per DAC. Since there are 2 DAC, the total datarate is 2x this meaning 10Gbps. However, splitting this data over 2 serdes lanes reduces each lane back to 5Gbps. This is regardless of the interpolation rate.

    Can you set register 0x51 to include a sync request on all 8 conditions? (0x51, 0xFF)

    After step 4, can you rewrite the 0x64 and 0x65 registers with value 0x0000 to clear the alarms, and then read the values of these registers? This register is "sticky" and will accumulate any errors as they come, so writing the register with 0x0000 to clear the alarms is needed before reading. The value in register 0x64 and 0x65 are for lanes 0 and 1, respectively.

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 10 points

    Hi Chase,

    We had thought that interpolation affects the data rate. What we're doing is starting with an input data rate of 125 MSPS, sent from a master Xilinx FPGA on two lanes running at a 2.5 Gbps line rate. This should mean that on the input side of the DAC (RX0/1 pins), Fdata = 125 MSPS.

    However, since we desire a DAC output rate of 250 MSPS, we're interpolating by 2. So we run the DAC CLK pins at 250 MHz. Are we mistaken in our approach? Is it possible you can send an example configuration?

    Here's the behavior of JESD Sync before the modification to register 0x51:

    Here's the behavior of JESD Sync after the modification to register 0x51:

    Here's the status of the two lane alarm registers:

    0x64: 0x0100
    0x65: 0x0100

    Both have a 8b/10b disparity error flag.

  • 0 in reply to Ashley G
    TI__Mastermind 23760 points

    Hi Ashley,

    My mistake. I read the original post as the datarate was 250M. The DACCLK will be 250MSPS in interpolation by 2 if the datarate is 125M. This does yield the correct 2.5Gbps lane rate.

    Are you using sysref at all? The registers seem to indicate not. For subclass 1, sysref should be used.

    A few other things from reviewing the register config:

    • Clock dividers are not being synced via any sysref pulse. Set it to align dividers on next sysref pulse (0x24 to value 0x20)
    • Try to set the unused lanes as link 1 rather than link 3. I suspect link 2/3 are not valid options for the dual device and the table may have been copied wrong from quad device. setting register 0x49 to value 0x5550 fixes this.
    • Set link0 configuration to skip one sysref then use the next. (set 0x5C to 0x3)
    • Output muxing is not correct. Right now, data path 0 goes to both IOUTA and IOUTD. to fix, set 0x22 from 0x101C to 0x102D. this makes data path 0 on IOUTA, data path 1 on IOUTD. And although they are not use, I have set data path 2 on IOUTB and data path 3 on IOUTC to avoid duplicate data path going to multiple dac outputs.

    Once the link is up, you can then disable the sysref output which is providing the signal to the DAC.

    Disparity errors usually occur when there is a timing mismatch between the device, whether ADC or DAC, and the FPGA. I could see how not aligning the JESD CLK or SERDES CLK to a common edge (SYSREF) could cause these issues.

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 10 points

    Hi Chase,

    We're sending 3 SYSREFs during initialization. We're still not able to get a JESD link up with your suggested register changes. A few questions...

    1. Is it possible to get a DAC configuration table from you that has the correct values for this setup? Maybe there's something we're missing in the configuration sequence.
    2. What is the best way to verify the device is seeing the SYSREFs and that they're occurring at the proper time?

    Thanks,
    Ashley

  • 0 in reply to Ashley G
    TI__Mastermind 23760 points

    Hi Ashley,

    I was out of office last week and have been catching up as fast as I can. I will see if there is any checks for this first thing in the morning. I will also generate a config for your 250MSPS 2x int mode and try to indicate what the sysref is doing at each point during the dac configuration sequence to see if that helps solve this issue. Stay tuned.

    Thanks, Chase

  • 0 in reply to Chase W
    TI__Mastermind 23760 points

    Hi Ashley,

    I have put together this config. I have tested it on my board and have left comments in the config file. I have also taken only the dac portion and placed it into your format above with your specific register values to the best of my knowledge. Please give this a try.

    250MSPS_2xint_drs_cw.cfg

    250MSPS_2xint_drs_DAC_reg.cfg

    Thanks, Chase