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ADC3424: LVDS DCLK frequency

菊井 良則
Prodigy 130 points
Part Number: ADC3424

Could you tell me about ADC3424 LVDS DCLK frequency?

It is fixed value? Or it is changed dynamically by analog input value?

Now, I wonder DCLK frequency is changing each our product operation.

Sometimes, it is about 370MHz, but it is about 190MHz.

(I don't change ADC register between this trying.)

Is this phenomenon reasonable?

Could you tell me how is LVDS DCLK frequency determined?

Thank you.

Yoshinori Kikui

  • 0
    TI__Intellectual 2280 points

    Hi Yoshinori,

    DCLK is not a fixed value; it's frequency is dependent upon the mode the part is in and upon the ADC sampling clock frequency.

    菊井 良則 said:

    Now, I wonder DCLK frequency is changing each our product operation.

    Sometimes, it is about 370MHz, but it is about 190MHz.

    Regarding this comment on DCLK changing, this does seem strange given there are not any register value changes being made. Is the input ADC sampling clock changing?

    DCLK frequency is determined by the ADC sampling clock and mode the device is in. For 12x serialization mode (One-wire) the DCLK is 6x the ADC sampling clock frequency and for 6x serialization mode (Two-wire; default) the DCLK is 3x the ADC sampling clock frequency. See the table below.

    Best regards,

    Drew

  • 0 in reply to Drew Harrell
    Prodigy 130 points

    Thank you for your answer.

    I understand DCLK frequency can't be changed without the change of input clock or ADC register (for detecting sampling clock rate).

    I will check the ADC register and our test condition.