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ADS1278 Oversampling Rate.

John Sotack
Intellectual 350 points

Other Parts Discussed in Thread: ADS1278

I am trying to use an ADS1278 EVM standalone in high resolution mode.  Under the following conditions, I get a data ready every 256 clocks rather than every 512 clocks. 

My ADS1278EVM settings are as follows:

SW11.1 = M0 = Off, SW11.2 = M1 = ON, SW11.3 = F0 = ON, SW11.4 = F1 = ON, SW11.5 = F2 = ON, SW11.6 = CLKDIV = 0FF.

For SW10, 1 & 2 are on and all other are off.

NN1, NP1, NN2, NP2 are all grounded, others float.

Channel switches are all toward ADC1278 chip.

SW1 set to ON BRD

TOUT = 7.87 MHZ

With the above settings, the frequency of the data ready pulse is 30.717 kHZ.  The expected value is TOUT/512 = 15.371 khz. 

For the actual rate of 30.717 khz, the master clock counts per point is 7.87/30.717 =  256.2 (within measurement error = 256).

If I move SW11.6 CLKDIV from OFF to ON, I get a 15.36 khz ~DATA READY pulse rate.

What settings are correct for high resolution mode?

What does CLKDIV do?

John

  • 0
    TI__Mastermind 43915 points

    Hi John,

    Take a look at Table 8 on page 26 of the data sheet. You will want to set the CLKDIV high in order to use High-Resolution mode where data is valid every 512 clocks.You will also want to make sure that the TEST pins are held low and the MODE[1:0] pins are set as 01.

    CLKDIV divides down the master clock for use as the modulator clock. When set high the clock is not divided and when set low, the clock is divided down. Dividing the clock is used to change the fclk/fdata ratio to give the user a little more flexibility with the data rate.

    Regards,

    Tony Calabria

  • 0
    Intellectual 740 points

    John,

    For high-resolution mode, CLKDIV must be 1.  Se tables 6 and 8 in the data sheet.  CLKDIV sets the modulator frequency as a ratio of the CLK signal.  From the data sheet, it appears that its use is restricted to only the low-speed and low-power modes.

    Matthew